clk_wiz.c File Reference

Clocking Wizard Userspace I/O Driver FreeBSD. More...

#include <sys/mman.h>
#include <sys/time.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include <unistd.h>
#include <fcntl.h>
#include "clk_wiz.h"

Data Structures
struct	clk_cfg

Macros
#define	ERR_MODE_INVALID   (0x0100U)
#define	ERR_NULL_PARAM   (0x0101U)
#define	CWIZ_REG_SOFT_RESET   (0x00000000U)
#define	CWIZ_REG_STATUS   (0x00000004U)
#define	CWIZ_REG_MON_ERR   (0x00000008U)
#define	CWIZ_REG_INT_STATUS   (0x0000000CU)
#define	CWIZ_REG_INT_ENABLE   (0x00000010U)
#define	CWIZ_REG_CLK_CONFIG   (0x00000200U)
#define	CWIZ_REG_CLK_FBPHASE   (0x00000204U)
#define	CWIZ_REG_CLKOUT0_DIVIDE   (0x00000208U)
#define	CWIZ_REG_CLKOUT0_PHASE   (0x0000020CU)
#define	CWIZ_REG_CLKOUT0_DUTY   (0x00000210U)
#define	CWIZ_REG_CONFIG_LOAD   (0x0000025CU)
#define	SOFT_RESET_VAL   (0x0000000AU)
#define	STATUS_LOCKED   (1 << 0)
#define	DIVCLK_DIVIDE_MASK   (0x000000FFU)
#define	CLKFBOUT_MULT_MASK   (0x0000FF00U)
#define	CLKFBOUT_FRAC_MASK   (0x03FF0000U)
#define	CLKOUT_DIVIDE_MASK   (0x000000FFU)
#define	CLKOUT_FRAC_SHIFT   (8)
#define	CLKOUT_FRAC_MASK   (0x0003FF00U)
#define	CONFIG_LOAD_SEN   (1 << 0)
#define	CONFIG_SADDR   (1 << 1)
#define	REG_READ(__BASE__, __OFFSET__)   *((volatile uint32_t *)(((uint8_t *)(__BASE__)) + (__OFFSET__)))
#define	REG_WRITE(__BASE__, __OFFSET__, __DATA__)   *((volatile uint32_t *)(((uint8_t *)(__BASE__)) + (__OFFSET__))) = (__DATA__)

Functions
int	clk_wiz_config (struct clk_wiz_dev *dev, enum clk_wiz_mode mode)
int	clk_wiz_init (struct clk_wiz_dev *dev, const char *devname)
	Video Timing Controller Initialization.

Detailed Description

Clocking Wizard Userspace I/O Driver FreeBSD.

Author

R. Bush bush@.nosp@m.krtk.nosp@m.l.com

Version

0.1

Date

August 6, 2018 Copyright (c) 2018, krtkl inc. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

The views and conclusions contained in the software and documentation are those of the authors and should not be interpreted as representing official policies, either expressed or implied, of the FreeBSD Project.

Macro Definition Documentation

CLKFBOUT_FRAC_MASK

#define CLKFBOUT_FRAC_MASK   (0x03FF0000U)

Multiplier fractional value

CLKFBOUT_MULT_MASK

#define CLKFBOUT_MULT_MASK   (0x0000FF00U)

Multiplier integer value

CLKOUT_DIVIDE_MASK

#define CLKOUT_DIVIDE_MASK   (0x000000FFU)

Clock out integer divide value

CLKOUT_FRAC_MASK

#define CLKOUT_FRAC_MASK   (0x0003FF00U)

Clock out fractional divide value

CWIZ_REG_CLK_CONFIG

#define CWIZ_REG_CLK_CONFIG   (0x00000200U)

Clock configuration

CWIZ_REG_CLK_FBPHASE

#define CWIZ_REG_CLK_FBPHASE   (0x00000204U)

Clock phase

CWIZ_REG_CLKOUT0_DIVIDE

#define CWIZ_REG_CLKOUT0_DIVIDE   (0x00000208U)

Clock out 0 divide

CWIZ_REG_CLKOUT0_DUTY

#define CWIZ_REG_CLKOUT0_DUTY   (0x00000210U)

Clock out 0 duty cycle

CWIZ_REG_CLKOUT0_PHASE

#define CWIZ_REG_CLKOUT0_PHASE   (0x0000020CU)

Clock out 0 phase

CWIZ_REG_CONFIG_LOAD

#define CWIZ_REG_CONFIG_LOAD   (0x0000025CU)

Clock configuration register 23

CWIZ_REG_INT_ENABLE

#define CWIZ_REG_INT_ENABLE   (0x00000010U)

Interrupt enable

CWIZ_REG_INT_STATUS

#define CWIZ_REG_INT_STATUS   (0x0000000CU)

Interrupt status

CWIZ_REG_MON_ERR

#define CWIZ_REG_MON_ERR   (0x00000008U)

Clock monitor error status

CWIZ_REG_SOFT_RESET

#define CWIZ_REG_SOFT_RESET   (0x00000000U)

Software reset

CWIZ_REG_STATUS

#define CWIZ_REG_STATUS   (0x00000004U)

Status

DIVCLK_DIVIDE_MASK

#define DIVCLK_DIVIDE_MASK   (0x000000FFU)

Divide value for all output clocks

SOFT_RESET_VAL

#define SOFT_RESET_VAL   (0x0000000AU)

Software reset value

STATUS_LOCKED

#define STATUS_LOCKED   (1 << 0)

MMCM/PLL locked status