vtc.c File Reference

Video Timing Controller Userspace I/O Driver FreeBSD. More...

#include <sys/mman.h>
#include <sys/time.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include <unistd.h>
#include <fcntl.h>
#include "vtc.h"

Data Structures
struct	vtc_polarity
struct	vtc_hoffset
struct	vtc_signal
struct	vtc_timing

Macros
#define	ERR_MODE_INVALID   (0x0100U)
#define	ERR_NULL_PARAM   (0x0101U)
#define	VTC_REG_CONTROL   (0x00000000U)
#define	VTC_REG_STATUS   (0x00000004U)
#define	VTC_REG_ERROR   (0x00000008U)
#define	VTC_REG_IRQ_ENABLE   (0x0000000CU)
#define	VTC_REG_VERSION   (0x00000010U)
#define	VTC_REG_DET_ASIZE   (0x00000020U)
#define	VTC_REG_DET_STATUS   (0x00000024U)
#define	VTC_REG_DET_ENC   (0x00000028U)
#define	VTC_REG_DET_POL   (0x0000002CU)
#define	VTC_REG_DET_HSIZE   (0x00000030U)
#define	VTC_REG_DET_VSIZE   (0x00000034U)
#define	VTC_REG_DET_HSYNC   (0x00000038U)
#define	VTC_REG_DET_VBLANK_F0   (0x0000003CU)
#define	VTC_REG_DET_VSYNC_V_F0   (0x00000040U)
#define	VTC_REG_DET_VSYNC_H_F0   (0x00000044U)
#define	VTC_REG_DET_VBLANK_F1   (0x00000048U)
#define	VTC_REG_DET_VSYNC_V_F1   (0x0000004CU)
#define	VTC_REG_DET_VSYNC_H_F1   (0x00000050U)
#define	VTC_REG_GEN_ASIZE   (0x00000060U)
#define	VTC_REG_GEN_STATUS   (0x00000064U)
#define	VTC_REG_GEN_ENC   (0x00000068U)
#define	VTC_REG_GEN_POL   (0x0000006CU)
#define	VTC_REG_GEN_HSIZE   (0x00000070U)
#define	VTC_REG_GEN_VSIZE   (0x00000074U)
#define	VTC_REG_GEN_HSYNC   (0x00000078U)
#define	VTC_REG_GEN_VBLANK_F0   (0x0000007CU)
#define	VTC_REG_GEN_VSYNC_V_F0   (0x00000080U)
#define	VTC_REG_GEN_VSYNC_H_F0   (0x00000084U)
#define	VTC_REG_GEN_VBLANK_F1   (0x00000088U)
#define	VTC_REG_GEN_VSYNC_V_F1   (0x0000008CU)
#define	VTC_REG_GEN_VSYNC_H_F1   (0x00000090U)
#define	CONTROL_SW_ENABLE   (1 << 0)
#define	CONTROL_REG_UPDATE   (1 << 1)
#define	CONTROL_GEN_ENABLE   (1 << 2)
#define	CONTROL_DET_ENABLE   (1 << 3)
#define	CONTROL_SYNC_ENABLE   (1 << 5)
#define	CONTROL_FRAME_HSIZE_SRC   (1 << 8)
#define	CONTROL_ACTIVE_HSIZE_SRC   (1 << 9)
#define	CONTROL_HSYNC_START_SRC   (1 << 10)
#define	CONTROL_HSYNC_END_SRC   (1 << 11)
#define	CONTROL_FRAME_VSIZE_SRC   (1 << 13)
#define	CONTROL_ACTIVE_VSIZE_SRC   (1 << 14)
#define	CONTROL_VSYNC_START_SRC   (1 << 15)
#define	CONTROL_VSYNC_END_SRC   (1 << 16)
#define	CONTROL_VBLANK_HOFF_SRC   (1 << 17)
#define	CONTROL_CHROMA_SRC   (1 << 18)
#define	CONTROL_VBLANK_POL_SRC   (1 << 20)
#define	CONTROL_HBLANK_POL_SRC   (1 << 21)
#define	CONTROL_VSYNC_POL_SRC   (1 << 22)
#define	CONTROL_HSYNC_POL_SRC   (1 << 23)
#define	CONTROL_ACTIVE_VIDEO_POL_SRC   (1 << 24)
#define	CONTROL_ACTIVE_CHROMA_POL_SRC   (1 << 25)
#define	CONTROL_FIELD_ID_POL_SRC   (1 << 26)
#define	CONTROL_FSYNC_RESET   (1 << 30)
#define	CONTROL_SW_RESET   (1 << 31)
#define	STATUS_LOCK   (1 << 8)
#define	STATUS_LOCK_LOSS   (1 << 9)
#define	STATUS_DET_VBLANK   (1 << 10)
#define	STATUS_DET_ACTIVE_VIDEO   (1 << 11)
#define	STATUS_GEN_VBLANK   (1 << 12)
#define	STATUS_GEN_ACTIVE_VIDEO   (1 << 13)
#define	STATUS_FSYNC_MASK   (0xFFFF0000U)
#define	ERROR_VBLANK_LOCK   (1 << 16)
#define	ERROR_HBLANK_LOCK   (1 << 17)
#define	ERROR_VSYNC_LOCK   (1 << 18)
#define	ERROR_HSYNC_LOCK   (1 << 19)
#define	ERROR_ACTIVE_VIDEO_LOCK   (1 << 20)
#define	ERROR_ACTIVE_CHROMA_LOCK   (1 << 21)
#define	IRQ_ENABLE_LOCK   (1 << 8)
#define	IRQ_ENABLE_LOCK_LOSS   (1 << 9)
#define	IRQ_ENABLE_DET_VBLANK   (1 << 10)
#define	IRQ_ENABLE_DET_ACTIVE_VIDEO   (1 << 11)
#define	IRQ_ENABLE_GEN_VBLANK   (1 << 12)
#define	IRQ_ENABLE_GEN_ACTIVE_VIDEO   (1 << 13)
#define	IRQ_ENABLE_FSYNC_MASK   (0xFFFF0000U)
#define	GEN_ASIZE_HSIZE   (0x00001FFFU)
#define	GEN_ASIZE_VSIZE   (0x1FFF0000U)
#define	GEN_STATUS_VBLANK   (1 << 1)
#define	GEN_STATUS_ACTIVE_VIDEO   (1 << 2)
#define	GEN_ENC_VIDEO_FORMAT_MASK   (0x000000FFU)
#define	GEN_ENC_INTERLACED   (1 << 6)
#define	GEN_ENC_FIELD_ID_PARITY   (1 << 7)
#define	GEN_ENC_CHROMA_PARITY_MASK   (0x00000300U)
#define	GEN_POL_VBLANK   (1 << 0)
#define	GEN_POL_HBLANK   (1 << 1)
#define	GEN_POL_VSYNC   (1 << 2)
#define	GEN_POL_HSYNC   (1 << 3)
#define	GEN_POL_ACTIVE_VIDEO   (1 << 4)
#define	GEN_POL_ACTIVE_CHROMA   (1 << 5)
#define	GEN_POL_FIELD_ID   (1 << 6)
#define	GEN_POL_ALL_MASK   (0x0000007FU)
#define	GEN_HSIZE_MASK   (0x00001FFFU)
#define	GEN_VSIZE_MASK   (0x00001FFFU)
#define	GEN_HSYNC_START_MASK   (0x00001FFFU)
#define	GEN_HSYNC_END_MASK   (0x1FFF0000U)
#define	GEN_VBLANK_HSTART_MASK   (0x00001FFFU)
#define	GEN_VBLANK_HEND_MASK   (0x1FFF0000U)
#define	GEN_VSYNC_VSTART_MASK   (0x00001FFFU)
#define	GEN_VSYNC_VEND_MASK   (0x1FFF0000U)
#define	GEN_VSYNC_HSTART_MASK   (0x00001FFFU)
#define	GEN_VSYNC_HEND_MASK   (0x1FFF0000U)
#define	REG_READ(__BASE__, __OFFSET__)   *((volatile uint32_t *)(((uint8_t *)(__BASE__)) + (__OFFSET__)))
#define	REG_WRITE(__BASE__, __OFFSET__, __DATA__)   *((volatile uint32_t *)(((uint8_t *)(__BASE__)) + (__OFFSET__))) = (__DATA__)
#define	GEN_POL_VBLANK   (1 << 0)
#define	GEN_POL_HBLANK   (1 << 1)
#define	GEN_POL_VSYNC   (1 << 2)
#define	GEN_POL_HSYNC   (1 << 3)
#define	GEN_POL_ACTIVE_VIDEO   (1 << 4)
#define	GEN_POL_ACTIVE_CHROMA   (1 << 5)
#define	GEN_POL_FIELD_ID   (1 << 6)

Functions
struct vtc_timing *	vtc_mode2tim (struct vtc_dev *dev, enum vtc_mode mode)
static void	vtc_write_start_end (struct vtc_dev *dev, uint32_t reg, uint32_t start, uint32_t end)
void	vtc_tim2sig (struct vtc_dev *dev, struct vtc_timing *timing, struct vtc_signal *signal, struct vtc_hoffset *hoffset, struct vtc_polarity *pol)
static int	vtc_reset (struct vtc_dev *dev)
int	vtc_enable (struct vtc_dev *dev, bool en)
	Enable Video Timing Controller. More...
int	vtc_gen_enable (struct vtc_dev *dev, bool en)
	Enable Video Timing Generator. More...
int	vtc_det_enable (struct vtc_dev *dev, bool en)
	Enable Video Timing Detector.
int	vtc_det_dump (struct vtc_dev *dev)
void	vtc_set_polarity (struct vtc_dev *dev, struct vtc_polarity *pol)
	Set Polarity.
uint32_t	vtc_get_version (struct vtc_dev *dev)
	Get Version.
static void	vtc_set_genenerator_hoffset (struct vtc_dev *dev, struct vtc_hoffset *hoffset)
static void	vtc_set_generator (struct vtc_dev *dev, struct vtc_signal *signal)
int	vtc_set_generator_timing (struct vtc_dev *dev, struct vtc_timing *timing)
	Set Video Timing Generator Timing.
int	vtc_set_generator_video_mode (struct vtc_dev *dev, enum vtc_mode mode)
	Set Video Generator Video Mode.
int	vtc_enable_interrupts (struct vtc_dev *dev)
int	vtc_init (struct vtc_dev *dev, const char *devname)
	Video Timing Controller Initialization.

Variables
static struct vtc_timing	video_timing []

Detailed Description

Video Timing Controller Userspace I/O Driver FreeBSD.

Author

R. Bush bush@.nosp@m.krtk.nosp@m.l.com

Version

0.1

Date

August 6, 2018 Copyright (c) 2018, krtkl inc. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

The views and conclusions contained in the software and documentation are those of the authors and should not be interpreted as representing official policies, either expressed or implied, of the FreeBSD Project.

Macro Definition Documentation

CONTROL_ACTIVE_CHROMA_POL_SRC

#define CONTROL_ACTIVE_CHROMA_POL_SRC   (1 << 25)

Active chroma polarity source select

CONTROL_ACTIVE_HSIZE_SRC

#define CONTROL_ACTIVE_HSIZE_SRC   (1 << 9)

Generator horizontal active size source select

CONTROL_ACTIVE_VIDEO_POL_SRC

#define CONTROL_ACTIVE_VIDEO_POL_SRC   (1 << 24)

Active video polarity source select

CONTROL_ACTIVE_VSIZE_SRC

#define CONTROL_ACTIVE_VSIZE_SRC   (1 << 14)

Generator vertical active size source select

CONTROL_CHROMA_SRC

#define CONTROL_CHROMA_SRC   (1 << 18)

Generator chroma polarity and encoding source select

CONTROL_DET_ENABLE

#define CONTROL_DET_ENABLE   (1 << 3)

Detection enable

CONTROL_FIELD_ID_POL_SRC

#define CONTROL_FIELD_ID_POL_SRC   (1 << 26)

Field ID polarity source select

CONTROL_FRAME_HSIZE_SRC

#define CONTROL_FRAME_HSIZE_SRC   (1 << 8)

Generator horizontal frame size source select

CONTROL_FRAME_VSIZE_SRC

#define CONTROL_FRAME_VSIZE_SRC   (1 << 13)

Generator vertical frame size source select

CONTROL_FSYNC_RESET

#define CONTROL_FSYNC_RESET   (1 << 30)

Frame Sync Core reset

CONTROL_GEN_ENABLE

#define CONTROL_GEN_ENABLE   (1 << 2)

Generation enable

CONTROL_HBLANK_POL_SRC

#define CONTROL_HBLANK_POL_SRC   (1 << 21)

Horizontal blank polarity source select

CONTROL_HSYNC_END_SRC

#define CONTROL_HSYNC_END_SRC   (1 << 11)

Generator horizontal sync end source select

CONTROL_HSYNC_POL_SRC

#define CONTROL_HSYNC_POL_SRC   (1 << 23)

Horizontal sync polarity source select

CONTROL_HSYNC_START_SRC

#define CONTROL_HSYNC_START_SRC   (1 << 10)

Generator horizontal sync start source select

CONTROL_REG_UPDATE

#define CONTROL_REG_UPDATE   (1 << 1)

Register update. Generator and Fsync registers are double-buffered.

CONTROL_SW_ENABLE

#define CONTROL_SW_ENABLE   (1 << 0)

Core enable

CONTROL_SW_RESET

#define CONTROL_SW_RESET   (1 << 31)

Core reset

CONTROL_SYNC_ENABLE

#define CONTROL_SYNC_ENABLE   (1 << 5)

Generator synchronization enable

CONTROL_VBLANK_HOFF_SRC

#define CONTROL_VBLANK_HOFF_SRC   (1 << 17)

Generator vertical blank offset source select

CONTROL_VBLANK_POL_SRC

#define CONTROL_VBLANK_POL_SRC   (1 << 20)

Vertical Blank Polarity Source Select

CONTROL_VSYNC_END_SRC

#define CONTROL_VSYNC_END_SRC   (1 << 16)

Generator vertical sync end source select

CONTROL_VSYNC_POL_SRC

#define CONTROL_VSYNC_POL_SRC   (1 << 22)

Vertical sync polarity source select

CONTROL_VSYNC_START_SRC

#define CONTROL_VSYNC_START_SRC   (1 << 15)

Generator vertical sync start source select

ERROR_ACTIVE_CHROMA_LOCK

#define ERROR_ACTIVE_CHROMA_LOCK   (1 << 21)

Active chroma lock status

ERROR_ACTIVE_VIDEO_LOCK

#define ERROR_ACTIVE_VIDEO_LOCK   (1 << 20)

Active video lock status

ERROR_HBLANK_LOCK

#define ERROR_HBLANK_LOCK   (1 << 17)

Horizontal blank lock status

ERROR_HSYNC_LOCK

#define ERROR_HSYNC_LOCK   (1 << 19)

Horizontal sync lock status

ERROR_VBLANK_LOCK

#define ERROR_VBLANK_LOCK   (1 << 16)

Vertical blank lock status

ERROR_VSYNC_LOCK

#define ERROR_VSYNC_LOCK   (1 << 18)

Vertical sync lock status

GEN_ASIZE_HSIZE

#define GEN_ASIZE_HSIZE   (0x00001FFFU)

Generated horizontal active frame size

GEN_ASIZE_VSIZE

#define GEN_ASIZE_VSIZE   (0x1FFF0000U)

Generated vertical active frame size

GEN_ENC_CHROMA_PARITY_MASK

#define GEN_ENC_CHROMA_PARITY_MASK   (0x00000300U)

Generated chroma parity

GEN_ENC_FIELD_ID_PARITY

#define GEN_ENC_FIELD_ID_PARITY   (1 << 7)

Generated field ID parity

GEN_ENC_INTERLACED

#define GEN_ENC_INTERLACED   (1 << 6)

Generated video interlaced format

GEN_ENC_VIDEO_FORMAT_MASK

#define GEN_ENC_VIDEO_FORMAT_MASK   (0x000000FFU)

Generated video format

GEN_HSIZE_MASK

#define GEN_HSIZE_MASK   (0x00001FFFU)

Generated horizontal frame size

GEN_HSYNC_END_MASK

#define GEN_HSYNC_END_MASK   (0x1FFF0000U)

Generated horizontal sync end end cycle index

GEN_HSYNC_START_MASK

#define GEN_HSYNC_START_MASK   (0x00001FFFU)

Generated horizontal sync end start cycle index

GEN_POL_ACTIVE_CHROMA [1/2]

#define GEN_POL_ACTIVE_CHROMA   (1 << 5)

Generated active chroma polarity

GEN_POL_ACTIVE_CHROMA [2/2]

#define GEN_POL_ACTIVE_CHROMA   (1 << 5)

Generated active chroma polarity

GEN_POL_ACTIVE_VIDEO [1/2]

#define GEN_POL_ACTIVE_VIDEO   (1 << 4)

Generated active video polarity

GEN_POL_ACTIVE_VIDEO [2/2]

#define GEN_POL_ACTIVE_VIDEO   (1 << 4)

Generated active video polarity

GEN_POL_ALL_MASK

#define GEN_POL_ALL_MASK   (0x0000007FU)

All polarity bits

GEN_POL_FIELD_ID [1/2]

#define GEN_POL_FIELD_ID   (1 << 6)

Generated field ID polarity

GEN_POL_FIELD_ID [2/2]

#define GEN_POL_FIELD_ID   (1 << 6)

Generated field ID polarity

GEN_POL_HBLANK [1/2]

#define GEN_POL_HBLANK   (1 << 1)

Generated horizontal blank polarity

GEN_POL_HBLANK [2/2]

#define GEN_POL_HBLANK   (1 << 1)

Generated horizontal blank polarity

GEN_POL_HSYNC [1/2]

#define GEN_POL_HSYNC   (1 << 3)

Generated horizontal sync polarity

GEN_POL_HSYNC [2/2]

#define GEN_POL_HSYNC   (1 << 3)

Generated horizontal sync polarity

GEN_POL_VBLANK [1/2]

#define GEN_POL_VBLANK   (1 << 0)

Generated vertical blank polarity

GEN_POL_VBLANK [2/2]

#define GEN_POL_VBLANK   (1 << 0)

Generated vertical blank polarity

GEN_POL_VSYNC [1/2]

#define GEN_POL_VSYNC   (1 << 2)

Generated vertical sync polarity

GEN_POL_VSYNC [2/2]

#define GEN_POL_VSYNC   (1 << 2)

Generated vertical sync polarity

GEN_STATUS_ACTIVE_VIDEO

#define GEN_STATUS_ACTIVE_VIDEO   (1 << 2)

Generated active video interrupt status

GEN_STATUS_VBLANK

#define GEN_STATUS_VBLANK   (1 << 1)

Generated vertical blank interrupt status

GEN_VBLANK_HEND_MASK

#define GEN_VBLANK_HEND_MASK   (0x1FFF0000U)

Generated vertical blank horizontal start end cycle index

GEN_VBLANK_HSTART_MASK

#define GEN_VBLANK_HSTART_MASK   (0x00001FFFU)

Generated vertical blank horizontal start start cycle index

GEN_VSIZE_MASK

#define GEN_VSIZE_MASK   (0x00001FFFU)

Generated vertical frame size

GEN_VSYNC_HEND_MASK

#define GEN_VSYNC_HEND_MASK   (0x1FFF0000U)

Generated vertical sync horizontal start end cycle index

GEN_VSYNC_HSTART_MASK

#define GEN_VSYNC_HSTART_MASK   (0x00001FFFU)

Generated vertical sync horizontal start start cycle index

GEN_VSYNC_VEND_MASK

#define GEN_VSYNC_VEND_MASK   (0x1FFF0000U)

Generated vertical sync vertical start end cycle index

GEN_VSYNC_VSTART_MASK

#define GEN_VSYNC_VSTART_MASK   (0x00001FFFU)

Generated vertical sync vertical start start cycle index

IRQ_ENABLE_DET_ACTIVE_VIDEO

#define IRQ_ENABLE_DET_ACTIVE_VIDEO   (1 << 11)

Detected active video interrupt enable

IRQ_ENABLE_DET_VBLANK

#define IRQ_ENABLE_DET_VBLANK   (1 << 10)

Detected vertical blank interrupt enable

IRQ_ENABLE_FSYNC_MASK

#define IRQ_ENABLE_FSYNC_MASK   (0xFFFF0000U)

Frame synchronization interrupt enable

IRQ_ENABLE_GEN_ACTIVE_VIDEO

#define IRQ_ENABLE_GEN_ACTIVE_VIDEO   (1 << 13)

Generated active video interrupt enable

IRQ_ENABLE_GEN_VBLANK

#define IRQ_ENABLE_GEN_VBLANK   (1 << 12)

Generated vertical blank interrupt enable

IRQ_ENABLE_LOCK

#define IRQ_ENABLE_LOCK   (1 << 8)

Lock interrupt enable

IRQ_ENABLE_LOCK_LOSS

#define IRQ_ENABLE_LOCK_LOSS   (1 << 9)

Loss-of-lock interrupt enable

STATUS_DET_ACTIVE_VIDEO

#define STATUS_DET_ACTIVE_VIDEO   (1 << 11)

Detected active video interrupt status

STATUS_DET_VBLANK

#define STATUS_DET_VBLANK   (1 << 10)

Detected vertival blank interrupt status

STATUS_FSYNC_MASK

#define STATUS_FSYNC_MASK   (0xFFFF0000U)

Fsync interrupt status

STATUS_GEN_ACTIVE_VIDEO

#define STATUS_GEN_ACTIVE_VIDEO   (1 << 13)

Generated active video interrupt status

STATUS_GEN_VBLANK

#define STATUS_GEN_VBLANK   (1 << 12)

Generated vertical blank interrupt status

STATUS_LOCK

#define STATUS_LOCK   (1 << 8)

Lock status

STATUS_LOCK_LOSS

#define STATUS_LOCK_LOSS   (1 << 9)

Loss-of-lock status

VTC_REG_CONTROL

#define VTC_REG_CONTROL   (0x00000000U)

Control

VTC_REG_DET_ASIZE

#define VTC_REG_DET_ASIZE   (0x00000020U)

Frame size (without blanking)

VTC_REG_DET_ENC

#define VTC_REG_DET_ENC   (0x00000028U)

Frame encoding

VTC_REG_DET_HSIZE

#define VTC_REG_DET_HSIZE   (0x00000030U)

Horizontal frame size (with blanking)

VTC_REG_DET_HSYNC

#define VTC_REG_DET_HSYNC   (0x00000038U)

Hsync start and end cycle index

VTC_REG_DET_POL

#define VTC_REG_DET_POL   (0x0000002CU)

Blanking/sync polarity

VTC_REG_DET_STATUS

#define VTC_REG_DET_STATUS   (0x00000024U)

Timing measurement status

VTC_REG_DET_VBLANK_F0

#define VTC_REG_DET_VBLANK_F0   (0x0000003CU)

Vblank start and end cycle index (field 0)

VTC_REG_DET_VBLANK_F1

#define VTC_REG_DET_VBLANK_F1   (0x00000048U)

Start and end cycle index of VBlank for field 1

VTC_REG_DET_VSIZE

#define VTC_REG_DET_VSIZE   (0x00000034U)

Vertical frame size (with blanking)

VTC_REG_DET_VSYNC_H_F0

#define VTC_REG_DET_VSYNC_H_F0   (0x00000044U)

Start and end cycle index of VSync for field 0

VTC_REG_DET_VSYNC_H_F1

#define VTC_REG_DET_VSYNC_H_F1   (0x00000050U)

Start and end cycle index of VSync for field 1

VTC_REG_DET_VSYNC_V_F0

#define VTC_REG_DET_VSYNC_V_F0   (0x00000040U)

Start and end line index of VSync for field 0

VTC_REG_DET_VSYNC_V_F1

#define VTC_REG_DET_VSYNC_V_F1   (0x0000004CU)

Start and end line index of VSync for field 1

VTC_REG_ERROR

#define VTC_REG_ERROR   (0x00000008U)

Status/error

VTC_REG_GEN_ASIZE

#define VTC_REG_GEN_ASIZE   (0x00000060U)

Generator frame size (without blanking) (R/W)

VTC_REG_GEN_ENC

#define VTC_REG_GEN_ENC   (0x00000068U)

Generator frame encoding (R/W)

VTC_REG_GEN_HSIZE

#define VTC_REG_GEN_HSIZE   (0x00000070U)

Generator horizontal frame size (with blanking) (R/W)

VTC_REG_GEN_HSYNC

#define VTC_REG_GEN_HSYNC   (0x00000078U)

Generator hsync start and end cycle index

VTC_REG_GEN_POL

#define VTC_REG_GEN_POL   (0x0000006CU)

Generator blank and sync polarities (R/W)

VTC_REG_GEN_STATUS

#define VTC_REG_GEN_STATUS   (0x00000064U)

Generator timing measurement status (RO)

VTC_REG_GEN_VBLANK_F0

#define VTC_REG_GEN_VBLANK_F0   (0x0000007CU)

Generator vblank start and end cycle index of vsync for field 0

VTC_REG_GEN_VBLANK_F1

#define VTC_REG_GEN_VBLANK_F1   (0x00000088U)

Generator vblank start and end line index of vsync for field 1

VTC_REG_GEN_VSIZE

#define VTC_REG_GEN_VSIZE   (0x00000074U)

Generator vertical frame size (with blanking) (R/W)

VTC_REG_GEN_VSYNC_H_F0

#define VTC_REG_GEN_VSYNC_H_F0   (0x00000084U)

Generator vsync start and end line index of vsync for field 0

VTC_REG_GEN_VSYNC_H_F1

#define VTC_REG_GEN_VSYNC_H_F1   (0x00000090U)

Generator vsync start and end cycle index of vsync for field 1

VTC_REG_GEN_VSYNC_V_F0

#define VTC_REG_GEN_VSYNC_V_F0   (0x00000080U)

Generator vsync start and end line index of vsync for field 0

VTC_REG_GEN_VSYNC_V_F1

#define VTC_REG_GEN_VSYNC_V_F1   (0x0000008CU)

Generator vsync start and end line index of vsync for field 1

VTC_REG_IRQ_ENABLE

#define VTC_REG_IRQ_ENABLE   (0x0000000CU)

Interrupt enable/clear

VTC_REG_STATUS

#define VTC_REG_STATUS   (0x00000004U)

Core/interrupt status

VTC_REG_VERSION

#define VTC_REG_VERSION   (0x00000010U)

Core version

Function Documentation

vtc_enable()

int vtc_enable	(	struct vtc_dev *	dev,
		bool	en
	)

Enable Video Timing Controller.

Parameters

dev	Video timing controller device structure pointer
en	Enable timing controller selection

Returns

None

{
    uint32_t reg_val;

    reg_val = REG_READ(dev->base, VTC_REG_CONTROL);

    if (en)
        reg_val |= CONTROL_SW_RESET;
    else
        reg_val &= ~(CONTROL_SW_RESET);

    REG_WRITE(dev->base, VTC_REG_CONTROL, reg_val);

    return 0;
}

vtc_gen_enable()

int vtc_gen_enable	(	struct vtc_dev *	dev,
		bool	en
	)

Enable Video Timing Generator.

Parameters

dev	Video timing controller device structure pointer
en	Enable generator selection

Returns

None

{
    uint32_t reg_val;

    reg_val = REG_READ(dev->base, VTC_REG_CONTROL);

    if (en)
        reg_val |= CONTROL_GEN_ENABLE;
    else
        reg_val &= ~(CONTROL_GEN_ENABLE);

    reg_val |= CONTROL_REG_UPDATE;

    REG_WRITE(dev->base, VTC_REG_CONTROL, reg_val);

    return 0;
}