snickerdoodle Platform Controller
firmware for STM32F0 platform controller
Device Firmware Upgrade

Functions

void sd_dfu_start (void)
 Enter Device Firmware Upgrade Mode Prepare device to enter system memory by disabling peripheral clocks, disable PLL, clear pending interrupts and disable interrupts. More...
 

Detailed Description

Function Documentation

◆ sd_dfu_start()

void sd_dfu_start ( void  )

#include <Src/sd_platform.c>

Enter Device Firmware Upgrade Mode Prepare device to enter system memory by disabling peripheral clocks, disable PLL, clear pending interrupts and disable interrupts.

Disable peripheral clocks

Disable PLL

Disable systick

Run to stack pointer and execute code from system memory

447 {
448  void (*boot_jump)(void);
449 
453  __GPIOA_CLK_DISABLE();
454  __GPIOB_CLK_DISABLE();
455  __GPIOC_CLK_DISABLE();
456  __GPIOD_CLK_DISABLE();
457  __GPIOE_CLK_DISABLE();
458  __GPIOF_CLK_DISABLE();
459 
463  RCC->CR |= (uint32_t)0x00000001; /* Set HSION bit */
464  RCC->CFGR &= (uint32_t)0x08FFB80C; /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
465  RCC->CR &= (uint32_t)0xFEF6FFFF; /* Reset HSEON, CSSON and PLLON bits */
466  RCC->CR &= (uint32_t)0xFFFBFFFF; /* Reset HSEBYP bit */
467  RCC->CFGR &= (uint32_t)0xFFC0FFFF; /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
468  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; /* Reset PREDIV1[3:0] bits */
469  RCC->CFGR3 &= (uint32_t)0xFFF0FEAC; /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
470  RCC->CR2 &= (uint32_t)0xFFFFFFFE; /* Reset HSI14 bit */
471  RCC->CIR = 0x00000000; /* Disable all interrupts */
472 
476  SysTick->CTRL = 0;
477  SysTick->LOAD = 0;
478  SysTick->VAL = 0;
479 
483  __set_MSP(BOOT_STACK_ADDR);
484  boot_jump = (void (*)(void))(*((uint32_t *)(SYS_MEM_START_ADDR + 4)));
485  boot_jump();
486  while (1);
487 }
#define BOOT_STACK_ADDR
Definition: sd_platform.h:78
#define SYS_MEM_START_ADDR
Definition: sd_platform.h:79