piSmasher Configuration Libraries
piSmasher peripheral device configuration libraries
Modules | Data Structures | Macros | Enumerations | Functions | Variables
TDA1997x HDMI Receiver

Modules

 TDA1997X_Audio
 

Data Structures

struct  tda1997x_info_any
 
struct  tda1997x_info_vs
 
struct  tda1997x_info_avi
 
struct  tda1997x_info_spd
 
struct  tda1997x_info_aud
 
struct  tda1997x_info_mps
 
union  tda1997x_infoframe
 
struct  tda1997x_mtp_seed
 
struct  tda1997x_irq_event
 TDA1997X interrupt event. More...
 
struct  tda1997x_irq_source
 
struct  tda1997x_vid_cfg
 TDA1997X video configuration. More...
 
struct  tda1997x_cfg
 TDA1997X driver configuration. More...
 
struct  tda1997x_dev
 TDA1997X device structure. More...
 

Macros

#define TDA1997X_HDCP_DDC_ADDR   (0x74U)
 
#define PAGE_ADDR(__PAGE__, __ADDR__)   (((__PAGE__) << 8) | ((__ADDR__) & 0xFFU))
 
#define PAGE_OF(__REG__)   ((uint8_t)(((__REG__) >> 8) & 0xFFU))
 
#define EDID_BLOCK_LENGTH   (127)
 
#define COLOR_CONV_MATRIX_LENGTH   (15)
 
#define MAN_SUS_HDMI_DIS_OUT_BUF   (1 << 7)
 
#define MAN_SUS_HDMI_ANA_PATH   (1 << 6)
 
#define MAN_SUS_HDMI_DIS_HDCP   (1 << 5)
 
#define MAN_SUS_HDMI_DIS_TMDS_ENC   (1 << 4)
 
#define MAN_SUS_HDMI_DIS_TMDS_FLOW   (1 << 3)
 
#define MAN_SUS_HDMI_RST_HDCP   (1 << 2)
 
#define MAN_SUS_HDMI_TMDS_ENC   (1 << 1)
 
#define MAN_SUS_HDMI_TMDS_FLOW   (1 << 0)
 
#define HDMI_SOFT_RESET_DC   (1 << 7)
 
#define INFO_RST_NACK_HDCP   (1 << 7)
 
#define INFO_RST_AUDIO_FIFO_CTRL   (1 << 5)
 
#define INFO_RST_AUDIO_FIFO   (1 << 4)
 
#define INFO_RST_AUDIO_FIFO_MASK   (0x30U)
 
#define INFO_RST_GAMUT   (1 << 3)
 
#define INFO_RST_AI   (1 << 2)
 
#define INFO_RST_INFOFRAME   (1 << 1)
 
#define INFO_RST_AUDIO   (1 << 0)
 
#define RATE_CTRL_REFTIM_ENABLE   (1 << 0)
 
#define SUS_ENABLE   RATE_CTRL_REFTIM_ENABLE
 
#define HDCP_CTRL_DECRYPTKEY_ON   (1 << 1)
 
#define HDCP_CTRL_ENABLE   (1 << 0)
 
#define HDCP_BCAPS_DEFAULT   (1 << 7)
 
#define HDCP_BCAPS_FAST_REAUTH   (1 << 0)
 
#define FILTERS_CTRL_PREFIL_MASK   (0x03U)
 
#define OF_CTRL_OUTPUT_ACTIVE   (1 << 7)
 
#define OF_CTRL_VIDEO_HIZ   (1 << 6)
 
#define OF_CTRL_BIT_5   (1 << 5)
 
#define OF_CTRL_BLANKING_INSERT   (1 << 4)
 
#define OF_CTRL_TIMINGREF_INSERT   (1 << 3)
 
#define OF_CTRL_FORMAT_MASK   (0x03U)
 
#define CLKOUT_CLK_DELAY_MASK   (0x70U)
 
#define CLKOUT_CTRL_TOGGLE_ON   (1 << 2)
 
#define CLKOUT_CLK_SEL_MASK   (0x03U)
 
#define VDP_CTRL_COMPDEL_BYPASS   (1 << 5)
 
#define VDP_CTRL_FORMATTER_BYPASS   (1 << 4)
 
#define VDP_CTRL_PREFILTER_BYPASS   (1 << 1)
 
#define VDP_CTRL_MATRIX_BYPASS   (1 << 0)
 
#define DE_FREF_SEL_DELAY_MASK   (0xF0U)
 
#define DE_FREF_SEL_PIX_QUAL   (1 << 3)
 
#define DE_FREF_SEL_POL_INV   (1 << 2)
 
#define DE_FREF_SEL_OUT_MASK   (0x03U)
 
#define HS_HREF_SEL_DELAY_MASK   (0xF0U)
 
#define HS_HREF_SEL_PIX_QUAL   (1 << 3)
 
#define HS_HREF_SEL_POL_INV   (1 << 2)
 
#define HS_HREF_SEL_OUT_MASK   (0x03U)
 
#define VS_VREF_SEL_DELAY_MASK   (0xF0U)
 
#define VS_VREF_SEL_PIX_QUAL   (1 << 3)
 
#define VS_VREF_SEL_POL_INV   (1 << 2)
 
#define VS_VREF_SEL_OUT_MASK   (0x03U)
 
#define INPUT_SEL_FORMAT_RESET   (1 << 7)
 
#define INPUT_SEL_HDMIOUT   (1 << 1)
 
#define INPUT_SEL_DIG_INPUT   (1 << 0)
 
#define INPUT_SEL_VDPR_FMT_MASK   (0x85U)
 
#define AUDIO_PATH_SP_FLAG_USED_BY_FIFO   (1 << 2)
 
#define AUDIO_PATH_LAYOUT_FORCED   (1 << 1)
 
#define AUDIO_PATH_LAYOUT_FORCED_1   (1 << 0)
 
#define AUDIO_SEL_ACLKINV   (1 << 7)
 
#define AUDIO_SEL_TESTTONE   (1 << 6)
 
#define AUDIO_SEL_SPDIF   (1 << 5)
 
#define AUDIO_SEL_I2S32   (1 << 4)
 
#define AUDIO_SEL_AUTOMUTE   (1 << 3)
 
#define AUDIO_SEL_HBR_DEMUX   (1 << 2)
 
#define AUDIO_SEL_MODE_MASK   (0x03U)
 
#define AUDIO_LAYOUT_SP_FLAG   (1 << 2)
 
#define AUDIO_LAYOUT_MANUAL   (1 << 1)
 
#define AUDIO_LAYOUT_LAYOUT_1   (1 << 0)
 
#define AUDIO_OUT_ENABLE_ACLK   (1 << 5)
 
#define AUDIO_OUT_ENABLE_WS   (1 << 4)
 
#define AUDIO_OUT_ENABLE_AP3   (1 << 3)
 
#define AUDIO_OUT_ENABLE_AP2   (1 << 2)
 
#define AUDIO_OUT_ENABLE_AP1   (1 << 1)
 
#define AUDIO_OUT_ENABLE_AP0   (1 << 0)
 
#define AUDIO_CLOCK_POWER_OFF   (1 << 7)
 
#define AUDIO_CLOCK_REF_TMDS   (1 << 6)
 
#define AUDIO_CLOCK_REF_FREQ_MASK   (0x03U << 4)
 
#define AUDIO_CLOCK_MODE_MASK   (0x07U)
 
#define AUDIO_FLAGS_HWMUTE   (1 << 7)
 
#define AUDIO_FLAGS_PACKET_MASK   (0x0FU)
 
#define IRQ_TOP_SUS   (1 << 0)
 
#define IRQ_TOP_DDC   (1 << 1)
 
#define IRQ_TOP_RATE   (1 << 2)
 
#define IRQ_TOP_MODE   (1 << 3)
 
#define IRQ_TOP_INFO   (1 << 4)
 
#define IRQ_TOP_AUDIO   (1 << 5)
 
#define IRQ_TOP_HDCP   (1 << 6)
 
#define IRQ_TOP_AFE   (1 << 7)
 
#define NIRQ_TOP_FLAGS   (8)
 
#define NIRQ_SOURCE_FLAGS   (8)
 
#define IRQ_SUS_MTP   (1 << 7)
 
#define IRQ_SUS_FORMAT   (1 << 5)
 
#define IRQ_SUS_RT_PULSE   (1 << 4)
 
#define IRQ_SUS_END   (1 << 3)
 
#define IRQ_SUS_ACTIVITY   (1 << 2)
 
#define IRQ_SUS_INPUT   (1 << 1)
 
#define IRQ_SUS_STATE   (1 << 0)
 
#define IRQ_DDC_EDID_MTP   (1 << 7)
 
#define IRQ_DDC_ERROR   (1 << 6)
 
#define IRQ_DDC_CMD_DONE   (1 << 5)
 
#define IRQ_DDC_READ_DONE   (1 << 4)
 
#define IRQ_DDC_RX_SW   (1 << 3)
 
#define IRQ_DDC_HDCP_SW   (1 << 2)
 
#define IRQ_DDC_PULSE_END   (1 << 1)
 
#define IRQ_DDC_DET_5V   (1 << 0)
 
#define IRQ_RATE_RXDB   (1 << 6)
 
#define IRQ_RATE_RXDA   (1 << 2)
 
#define IRQ_MODE_FLAGS   (1 << 7)
 
#define IRQ_MODE_GAMUT   (1 << 6)
 
#define IRQ_MODE_ISRC2   (1 << 5)
 
#define IRQ_MODE_ISRC1   (1 << 4)
 
#define IRQ_MODE_ACP   (1 << 3)
 
#define IRQ_MODE_DC_CHANGE   (1 << 0)
 
#define IRQ_INFO_MPS   (1 << 6)
 
#define IRQ_INFO_AUD   (1 << 5)
 
#define IRQ_INFO_SPD   (1 << 4)
 
#define IRQ_INFO_AVI   (1 << 3)
 
#define IRQ_INFO_VS_OTHER_BK2   (1 << 2)
 
#define IRQ_INFO_VS_OTHER_BK1   (1 << 1)
 
#define IRQ_INFO_VS   (1 << 0)
 
#define IRQ_AUDIO_FREQ_CHANGE   (1 << 5)
 
#define IRQ_AUDIO_FLAGS   (1 << 4)
 
#define IRQ_AUDIO_MUTE   (1 << 3)
 
#define IRQ_AUDIO_CHAN_STATUS   (1 << 2)
 
#define IRQ_AUDIO_FIFO_UNMUTE   (1 << 1)
 
#define IRQ_AUDIO_FIFO_ERROR   (1 << 0)
 
#define IRQ_HDCP_MTP   (1 << 7)
 
#define IRQ_HDCP_DLMTP   (1 << 4)
 
#define IRQ_HDCP_STATE_C5   (1 << 1)
 
#define IRQ_AFE_WDL_UNLOCKED   (1 << 7)
 
#define IRQ_AFE_GAIN_DONE   (1 << 6)
 
#define IRQ_AFE_OFFSET_DONE   (1 << 5)
 
#define IRQ_AFE_ACTIVITY_DET   (1 << 4)
 
#define IRQ_AFE_PLL_LOCK   (1 << 3)
 
#define IRQ_AFE_TRMCAL_DONE   (1 << 2)
 
#define IRQ_AFE_ASU_STATE   (1 << 1)
 
#define IRQ_AFE_ASU_READY   (1 << 0)
 
#define SUS_STATUS_STATE_MASK   (0x1FU)
 
#define SUS_STATUS_STATE   (1 << 4)
 
#define SUS_STATUS_CLK_STABLE   (1 << 2)
 
#define SUS_STATUS_CLK_ACTIVE   (1 << 1)
 
#define SUS_STATUS_LAST_STATE   (SUS_STATUS_STATE | (1 << 3) | SUS_STATUS_CLK_ACTIVE | (1 << 0))
 
#define VP_CTRL_LOZ   (0x00U)
 
#define VP_CTRL_HIZ   (0x40U)
 
#define VP_CTRL_A_LSB   (0xC0U)
 
#define VP_CTRL_A_ISB   (0xC1U)
 
#define VP_CTRL_A_MSB   (0xC2U)
 
#define VP_CTRL_B_LSB   (0xC3U)
 
#define VP_CTRL_B_ISB   (0xC4U)
 
#define VP_CTRL_B_MSB   (0xC5U)
 
#define VP_CTRL_C_LSB   (0xC6U)
 
#define VP_CTRL_C_ISB   (0xC7U)
 
#define VP_CTRL_C_MSB   (0xC8U)
 
#define VP_CTRL_RED_LSB   VP_CTRL_A_LSB
 
#define VP_CTRL_RED_ISB   VP_CTRL_A_ISB
 
#define VP_CTRL_RED_MSB   VP_CTRL_A_MSB
 
#define VP_CTRL_BLUE_LSB   VP_CTRL_B_LSB
 
#define VP_CTRL_BLUE_ISB   VP_CTRL_B_ISB
 
#define VP_CTRL_BLUE_MSB   VP_CTRL_B_MSB
 
#define VP_CTRL_GREEN_LSB   VP_CTRL_C_LSB
 
#define VP_CTRL_GREEN_ISB   VP_CTRL_C_ISB
 
#define VP_CTRL_GREEN_MSB   VP_CTRL_C_MSB
 
#define VP_CTRL_CBCR_LSB   VP_CTRL_A_LSB
 
#define VP_CTRL_CBCR_ISB   VP_CTRL_A_ISB
 
#define VP_CTRL_CBCR_MSB   VP_CTRL_A_MSB
 
#define VP_CTRL_CB_LSB   VP_CTRL_B_LSB
 
#define VP_CTRL_CB_ISB   VP_CTRL_B_ISB
 
#define VP_CTRL_CB_MSB   VP_CTRL_B_MSB
 
#define VP_CTRL_Y_LSB   VP_CTRL_C_LSB
 
#define VP_CTRL_Y_ISB   VP_CTRL_C_ISB
 
#define VP_CTRL_Y_MSB   VP_CTRL_C_MSB
 
#define PIX_REPEAT_UP_SEL_MASK   (0x30U)
 
#define PIX_REPEAT_PIX_REP_MASK   (0x0FU)
 
#define HPD_POWER_BYPASS_MASK   (0x0CU)
 
#define HPD_POWER_EDID_ONLY   (1 << 1)
 
#define HPD_AUTO_READ_EDID   (1 << 7)
 
#define HPD_AUTO_F3TECH   (1 << 5)
 
#define HPD_AUTO_OTHER   (1 << 4)
 
#define HPD_AUTO_UNSEL   (1 << 3)
 
#define HPD_AUTO_ALL_CHAN   (1 << 2)
 
#define HPD_AUTO_PREV_CHAN   (1 << 1)
 
#define HPD_AUTO_NEW_CHAN   (1 << 0)
 
#define HPD_MAN_GAIN_MASK   (0x03U)
 
#define HDMI_FLAGS_AUDIO   (1 << 7)
 
#define HDMI_FLAGS_HDMI   (1 << 6)
 
#define HDMI_FLAGS_EESS   (1 << 5)
 
#define HDMI_FLAGS_HDCP   (1 << 4)
 
#define HDMI_FLAGS_AVMUTE   (1 << 3)
 
#define HDMI_FLAGS_AUD_LAYOUT   (1 << 2)
 
#define HDMI_FLAGS_AUD_FIFO_OVR   (1 << 1)
 
#define HDMI_FLAGS_AUD_FIFO_LOW   (1 << 0)
 
#define HDMI_CTRL_MUTE_MASK   (0x0CU)
 
#define HMTP_CNTRL_DL_ALL   (1 << 0)
 
#define HDMI_CTRL_HDCP_MASK   (0x03U)
 
#define INFO_AUD_CODE_TYPE_MASK   (0xF0U)
 
#define INFO_AUD_CH_COUNT_MASK   (0x07U)
 
#define INFO_AUD_SAMPLE_FREQ_MASK   (0x1CU)
 
#define INFO_AUD_SAMPLE_SIZE_MASK   (0x03U)
 
#define INFO_AUD_CODE_EXT_MASK   (0x1FU)
 
#define INFO_AUD_DM_INHIBIT   (1 << 7)
 
#define INFO_AUD_LVL_SHIFT_MASK   (0x78U)
 
#define INFO_AUD_LFE_PB_MASK   (0x03U)
 
#define TDA1997X_SEED_TABLE_LEN   (10)
 

Enumerations

enum  clkout_clk_sel { CLKOUT_CLK_SEL_PCLK = 0x00, CLKOUT_CLK_SEL_PCLK_X2 = 0x01, CLKOUT_CLK_SEL_PCLK_DIV2 = 0x02, CLKOUT_CLK_SEL_PCLK_DIV4 = 0x03 }
 
enum  de_fref_sel { DE_FREF_SEL_OUT_DE_VHREF = 0x00, DE_FREF_SEL_OUT_FREF_VHREF = 0x01, DE_FREF_SEL_OUT_FREF_HDMI = 0x02 }
 
enum  hs_href_sel { HS_HREF_SEL_OUT_HS_VHREF = 0x00, HS_HREF_SEL_OUT_HREF_VHREF = 0x01, HS_HREF_SEL_OUT_HREF_HDMI = 0x02, HS_HREF_SEL_OUT_NOT_GENERATED = 0x03 }
 
enum  vs_vref_sel { VS_VREF_SEL_OUT_VS_VHREF = 0x00, VS_VREF_SEL_OUT_VREF_VHREF = 0x01, VS_VREF_SEL_OUT_VREF_HDMI = 0x02, VS_VREF_SEL_OUT_NOT_GENERATED = 0x03 }
 
enum  audio_clock_ref_freq { AUDIO_CLOCK_REF_FREQ_13_5MHz = 0x00, AUDIO_CLOCK_REF_FREQ_27MHz = 0x10, AUDIO_CLOCK_REF_FREQ_54MHz = 0x20 }
 
enum  audio_clock_mode {
  AUDIO_CLOCK_MODE_16FS = 0x00, AUDIO_CLOCK_MODE_32FS = 0x01, AUDIO_CLOCK_MODE_64FS = 0x02, AUDIO_CLOCK_MODE_128FS = 0x03,
  AUDIO_CLOCK_MODE_256FS = 0x04, AUDIO_CLOCK_MODE_512FS = 0x05
}
 
enum  audio_flags_packet {
  AUDIO_FLAGS_PACKET_NONE = 0x00, AUDIO_FLAGS_PACKET_SAMPLE = 0x01, AUDIO_FLAGS_PACKET_HBR = 0x02, AUDIO_FLAGS_PACKET_OBA = 0x04,
  AUDIO_FLAGS_PACKET_DST = 0x08
}
 
enum  pix_repeat_up_sel { PIX_REPEAT_UP_SEL_BYPASS = 0x00, PIX_REPEAT_UP_SEL_REPEATCHROMA = 0x10, PIX_REPEAT_UP_SEL_INTERPOLATE = 0x20 }
 
enum  hdmi_ctrl_mute { HDMI_CTRL_MUTE_AUTO = 0x00, HDMI_CTRL_MUTE_OFF = 0x04, HDMI_CTRL_MUTE_ON = 0x08 }
 
enum  hdmi_ctrl_hdcp { HDMI_CTRL_HDCP_AUTO = 0x00, HDMI_CTRL_HDCP_OESS = 0x01, HDMI_CTRL_HDCP_EESS = 0x02 }
 
enum  page {
  PAGE_CTRL = 0x00, PAGE_HDMI = 0x01, PAGE_AVI = 0x02, PAGE_TMDSA = 0x12,
  PAGE_TMDSB = 0x13, PAGE_14 = 0x14, PAGE_EDIDA = 0x20, PAGE_EDIDB = 0x21,
  PAGE_CMTP = 0x30, PAGE_MTPA = 0x40, PAGE_MTPB = 0x41, PAGE_MTPC = 0x42,
  PAGE_INVALID = 0xFF
}
 
enum  hdmi_reg {
  VERSION = PAGE_ADDR(PAGE_CTRL, 0x00), INPUT_SEL = PAGE_ADDR(PAGE_CTRL, 0x01), SERVICE_MODE = PAGE_ADDR(PAGE_CTRL, 0x02), HPD_MAN_CTRL = PAGE_ADDR(PAGE_CTRL, 0x03),
  RT_MAN_CTRL = PAGE_ADDR(PAGE_CTRL, 0x04), MANUAL_PD_DDC = PAGE_ADDR(PAGE_CTRL, 0x05), MANUAL_PD_TMDS = PAGE_ADDR(PAGE_CTRL, 0x06), MANUAL_PD_VDP = PAGE_ADDR(PAGE_CTRL, 0x07),
  MANUAL_PD_ADP = PAGE_ADDR(PAGE_CTRL, 0x08), DDC_SOFT_RST = PAGE_ADDR(PAGE_CTRL, 0x09), STANDBY_SOFT_RST = PAGE_ADDR(PAGE_CTRL, 0x0A), HDMI_SOFT_RST = PAGE_ADDR(PAGE_CTRL, 0x0B),
  HDMI_INFO_RST = PAGE_ADDR(PAGE_CTRL, 0x0C), IRQ_FLG_CLR_TOP = PAGE_ADDR(PAGE_CTRL, 0x0E), IRQ_FLG_CLR_SUS = PAGE_ADDR(PAGE_CTRL, 0x0F), IRQ_FLG_CLR_DDC = PAGE_ADDR(PAGE_CTRL, 0x10),
  IRQ_FLG_CLR_RATE = PAGE_ADDR(PAGE_CTRL, 0x11), IRQ_FLG_CLR_MODE = PAGE_ADDR(PAGE_CTRL, 0x12), IRQ_FLG_CLR_INFO = PAGE_ADDR(PAGE_CTRL, 0x13), IRQ_FLG_CLR_AUDIO = PAGE_ADDR(PAGE_CTRL, 0x14),
  IRQ_FLG_CLR_HDCP = PAGE_ADDR(PAGE_CTRL, 0x15), IRQ_FLG_CLR_AFE = PAGE_ADDR(PAGE_CTRL, 0x16), IRQ_MASK_TOP = PAGE_ADDR(PAGE_CTRL, 0x17), IRQ_MASK_SUS = PAGE_ADDR(PAGE_CTRL, 0x18),
  IRQ_MASK_DDC = PAGE_ADDR(PAGE_CTRL, 0x19), IRQ_MASK_RATE = PAGE_ADDR(PAGE_CTRL, 0x1A), IRQ_MASK_MODE = PAGE_ADDR(PAGE_CTRL, 0x1B), IRQ_MASK_INFO = PAGE_ADDR(PAGE_CTRL, 0x1C),
  IRQ_MASK_AUDIO = PAGE_ADDR(PAGE_CTRL, 0x1D), IRQ_MASK_HDCP = PAGE_ADDR(PAGE_CTRL, 0x1E), IRQ_MASK_AFE = PAGE_ADDR(PAGE_CTRL, 0x1F), DETECT_5V_HPD = PAGE_ADDR(PAGE_CTRL, 0x20),
  SUS_STATUS = PAGE_ADDR(PAGE_CTRL, 0x21), V_PER_MSB = PAGE_ADDR(PAGE_CTRL, 0x22), V_PER_ISB = PAGE_ADDR(PAGE_CTRL, 0x23), V_PER_LSB = PAGE_ADDR(PAGE_CTRL, 0x24),
  H_PER_MSB = PAGE_ADDR(PAGE_CTRL, 0x25), H_PER_LSB = PAGE_ADDR(PAGE_CTRL, 0x26), HS_WIDTH_MSB = PAGE_ADDR(PAGE_CTRL, 0x27), HS_WIDTH_LSB = PAGE_ADDR(PAGE_CTRL, 0x28),
  FMT_H_TOT_MSB = PAGE_ADDR(PAGE_CTRL, 0x29), FMT_H_TOT_LSB = PAGE_ADDR(PAGE_CTRL, 0x2A), FMT_H_ACT_MSB = PAGE_ADDR(PAGE_CTRL, 0x2B), FMT_H_ACT_LSB = PAGE_ADDR(PAGE_CTRL, 0x2C),
  FMT_H_FRONT_MSB = PAGE_ADDR(PAGE_CTRL, 0x2D), FMT_H_FRONT_LSB = PAGE_ADDR(PAGE_CTRL, 0x2E), FMT_H_SYNC_MSB = PAGE_ADDR(PAGE_CTRL, 0x2F), FMT_H_SYNC_LSB = PAGE_ADDR(PAGE_CTRL, 0x30),
  FMT_H_BACK_MSB = PAGE_ADDR(PAGE_CTRL, 0x31), FMT_H_BACK_LSB = PAGE_ADDR(PAGE_CTRL, 0x32), FMT_V_TOT_MSB = PAGE_ADDR(PAGE_CTRL, 0x33), FMT_V_TOT_LSB = PAGE_ADDR(PAGE_CTRL, 0x34),
  FMT_V_ACT_MSB = PAGE_ADDR(PAGE_CTRL, 0x35), FMT_V_ACT_LSB = PAGE_ADDR(PAGE_CTRL, 0x36), FMT_V_FRONT_F1 = PAGE_ADDR(PAGE_CTRL, 0x37), FMT_V_FRONT_F2 = PAGE_ADDR(PAGE_CTRL, 0x38),
  FMT_V_SYNC = PAGE_ADDR(PAGE_CTRL, 0x39), FMT_V_BACK_F1 = PAGE_ADDR(PAGE_CTRL, 0x3A), FMT_V_BACK_F2 = PAGE_ADDR(PAGE_CTRL, 0x3B), FMT_DE_ACT = PAGE_ADDR(PAGE_CTRL, 0x3C),
  EQ_STATUS0 = PAGE_ADDR(PAGE_CTRL, 0x3E), EQ_STATUS1 = PAGE_ADDR(PAGE_CTRL, 0x3F), RATE_CTRL = PAGE_ADDR(PAGE_CTRL, 0x40), RATE_DELTA = PAGE_ADDR(PAGE_CTRL, 0x41),
  RATE_STABLE_CNT = PAGE_ADDR(PAGE_CTRL, 0x42), CLK_MIN_RATE_MSB = PAGE_ADDR(PAGE_CTRL, 0x43), CLK_MIN_RATE_ISB = PAGE_ADDR(PAGE_CTRL, 0x44), CLK_MIN_RATE_LSB = PAGE_ADDR(PAGE_CTRL, 0x45),
  CLK_MAX_RATE_MSB = PAGE_ADDR(PAGE_CTRL, 0x46), CLK_MAX_RATE_ISB = PAGE_ADDR(PAGE_CTRL, 0x47), CLK_MAX_RATE_LSB = PAGE_ADDR(PAGE_CTRL, 0x48), CLK_A_STATUS = PAGE_ADDR(PAGE_CTRL, 0x49),
  CLK_A_RATE_MSB = PAGE_ADDR(PAGE_CTRL, 0x4A), CLK_A_RATE_ISB = PAGE_ADDR(PAGE_CTRL, 0x4B), CLK_A_RATE_LSB = PAGE_ADDR(PAGE_CTRL, 0x4C), DRIFT_CLK_A_REG = PAGE_ADDR(PAGE_CTRL, 0x4D),
  CLK_B_STATUS = PAGE_ADDR(PAGE_CTRL, 0x4E), CLK_B_RATE_MSB = PAGE_ADDR(PAGE_CTRL, 0x4F), CLK_B_RATE_ISB = PAGE_ADDR(PAGE_CTRL, 0x50), CLK_B_RATE_LSB = PAGE_ADDR(PAGE_CTRL, 0x51),
  DRIFT_CLK_B_REG = PAGE_ADDR(PAGE_CTRL, 0x52), HDCP_CTRL = PAGE_ADDR(PAGE_CTRL, 0x60), HDCP_KDS_MSB = PAGE_ADDR(PAGE_CTRL, 0x61), HDCP_KDS_LSB = PAGE_ADDR(PAGE_CTRL, 0x62),
  HDCP_BCAPS = PAGE_ADDR(PAGE_CTRL, 0x63), HDCP_KEY_CTRL = PAGE_ADDR(PAGE_CTRL, 0x64), HDCP_BSTATUS_MSB = PAGE_ADDR(PAGE_CTRL, 0x65), HDCP_BSTATUS_LSB = PAGE_ADDR(PAGE_CTRL, 0x66),
  FIFO_KSV_IDX = PAGE_ADDR(PAGE_CTRL, 0x67), FIFO_KSV4 = PAGE_ADDR(PAGE_CTRL, 0x68), FIFO_KSV3 = PAGE_ADDR(PAGE_CTRL, 0x69), FIFO_KSV2 = PAGE_ADDR(PAGE_CTRL, 0x6A),
  FIFO_KSV1 = PAGE_ADDR(PAGE_CTRL, 0x6B), FIFO_KSV0 = PAGE_ADDR(PAGE_CTRL, 0x6C), HDCP_RPT_CTRL = PAGE_ADDR(PAGE_CTRL, 0x6D), INFO_CTRL = PAGE_ADDR(PAGE_CTRL, 0x76),
  INFO_EXCEED = PAGE_ADDR(PAGE_CTRL, 0x77), ACP_TIMEOUT = PAGE_ADDR(PAGE_CTRL, 0x78), PACKET_TYPE_SCAN = PAGE_ADDR(PAGE_CTRL, 0x79), PIX_REPEAT = PAGE_ADDR(PAGE_CTRL, 0x7B),
  AUDIO_PATH = PAGE_ADDR(PAGE_CTRL, 0x7C), AUDIO_SEL = PAGE_ADDR(PAGE_CTRL, 0x7D), AUDIO_OUT_ENABLE = PAGE_ADDR(PAGE_CTRL, 0x7E), AUDIO_OUT_LOW_HIZ = PAGE_ADDR(PAGE_CTRL, 0x7F),
  VDP_CTRL = PAGE_ADDR(PAGE_CTRL, 0x80), MAT_OI1_MSB = PAGE_ADDR(PAGE_CTRL, 0x81), MAT_OI1_LSB = PAGE_ADDR(PAGE_CTRL, 0x82), MAT_OI2_MSB = PAGE_ADDR(PAGE_CTRL, 0x83),
  MAT_OI2_LSB = PAGE_ADDR(PAGE_CTRL, 0x84), MAT_OI3_MSB = PAGE_ADDR(PAGE_CTRL, 0x85), MAT_OI3_LSB = PAGE_ADDR(PAGE_CTRL, 0x86), MAT_P11_MSB = PAGE_ADDR(PAGE_CTRL, 0x87),
  MAT_P11_LSB = PAGE_ADDR(PAGE_CTRL, 0x88), MAT_P12_MSB = PAGE_ADDR(PAGE_CTRL, 0x89), MAT_P12_LSB = PAGE_ADDR(PAGE_CTRL, 0x8A), MAT_P13_MSB = PAGE_ADDR(PAGE_CTRL, 0x8B),
  MAT_P13_LSB = PAGE_ADDR(PAGE_CTRL, 0x8C), MAT_P21_MSB = PAGE_ADDR(PAGE_CTRL, 0x8D), MAT_P21_LSB = PAGE_ADDR(PAGE_CTRL, 0x8E), MAT_P22_MSB = PAGE_ADDR(PAGE_CTRL, 0x8F),
  MAT_P22_LSB = PAGE_ADDR(PAGE_CTRL, 0x90), MAT_P23_MSB = PAGE_ADDR(PAGE_CTRL, 0x91), MAT_P23_LSB = PAGE_ADDR(PAGE_CTRL, 0x92), MAT_P31_MSB = PAGE_ADDR(PAGE_CTRL, 0x93),
  MAT_P31_LSB = PAGE_ADDR(PAGE_CTRL, 0x94), MAT_P32_MSB = PAGE_ADDR(PAGE_CTRL, 0x95), MAT_P32_LSB = PAGE_ADDR(PAGE_CTRL, 0x96), MAT_P33_MSB = PAGE_ADDR(PAGE_CTRL, 0x97),
  MAT_P33_LSB = PAGE_ADDR(PAGE_CTRL, 0x98), MAT_OO1_MSB = PAGE_ADDR(PAGE_CTRL, 0x99), MAT_OO1_LSB = PAGE_ADDR(PAGE_CTRL, 0x9A), MAT_OO2_MSB = PAGE_ADDR(PAGE_CTRL, 0x9B),
  MAT_OO2_LSB = PAGE_ADDR(PAGE_CTRL, 0x9C), MAT_OO3_MSB = PAGE_ADDR(PAGE_CTRL, 0x9D), MAT_OO3_LSB = PAGE_ADDR(PAGE_CTRL, 0x9E), VHREF_CTRL = PAGE_ADDR(PAGE_CTRL, 0xA0),
  PXCNT_PR_MSB = PAGE_ADDR(PAGE_CTRL, 0xA2), PXCNT_PR_LSB = PAGE_ADDR(PAGE_CTRL, 0xA3), PXCNT_NPIX_MSB = PAGE_ADDR(PAGE_CTRL, 0xA4), PXCNT_NPIX_LSB = PAGE_ADDR(PAGE_CTRL, 0xA5),
  LCNT_PR_MSB = PAGE_ADDR(PAGE_CTRL, 0xA6), LCNT_PR_LSB = PAGE_ADDR(PAGE_CTRL, 0xA7), LCNT_NLIN_MSB = PAGE_ADDR(PAGE_CTRL, 0xA8), LCNT_NLIN_LSB = PAGE_ADDR(PAGE_CTRL, 0xA9),
  HREF_S_MSB = PAGE_ADDR(PAGE_CTRL, 0xAA), HREF_S_LSB = PAGE_ADDR(PAGE_CTRL, 0xAB), HREF_E_MSB = PAGE_ADDR(PAGE_CTRL, 0xAC), HREF_E_LSB = PAGE_ADDR(PAGE_CTRL, 0xAD),
  HS_S_MSB = PAGE_ADDR(PAGE_CTRL, 0xAE), HS_S_LSB = PAGE_ADDR(PAGE_CTRL, 0xAF), HS_E_MSB = PAGE_ADDR(PAGE_CTRL, 0xB0), HS_E_LSB = PAGE_ADDR(PAGE_CTRL, 0xB1),
  VREF_F1_S_MSB = PAGE_ADDR(PAGE_CTRL, 0xB2), VREF_F1_S_LSB = PAGE_ADDR(PAGE_CTRL, 0xB3), VREF_F1_WIDTH = PAGE_ADDR(PAGE_CTRL, 0xB4), VREF_F2_S_MSB = PAGE_ADDR(PAGE_CTRL, 0xB5),
  VREF_F2_S_LSB = PAGE_ADDR(PAGE_CTRL, 0xB6), VREF_F2_WIDTH = PAGE_ADDR(PAGE_CTRL, 0xB7), VS_F1_LINE_S_MSB = PAGE_ADDR(PAGE_CTRL, 0xB8), VS_F1_LINE_S_LSB = PAGE_ADDR(PAGE_CTRL, 0xB9),
  VS_F1_LINE_WIDTH = PAGE_ADDR(PAGE_CTRL, 0xBA), VS_F2_LINE_S_MSB = PAGE_ADDR(PAGE_CTRL, 0xBB), VS_F2_LINE_S_LSB = PAGE_ADDR(PAGE_CTRL, 0xBC), VS_F2_LINE_WIDTH = PAGE_ADDR(PAGE_CTRL, 0xBD),
  VS_F1_PIX_S_MSB = PAGE_ADDR(PAGE_CTRL, 0xBE), VS_F1_PIX_S_LSB = PAGE_ADDR(PAGE_CTRL, 0xBF), VS_F1_PIX_E_MSB = PAGE_ADDR(PAGE_CTRL, 0xC0), VS_F1_PIX_E_LSB = PAGE_ADDR(PAGE_CTRL, 0xC1),
  VS_F2_PIX_S_MSB = PAGE_ADDR(PAGE_CTRL, 0xC2), VS_F2_PIX_S_LSB = PAGE_ADDR(PAGE_CTRL, 0xC3), VS_F2_PIX_E_MSB = PAGE_ADDR(PAGE_CTRL, 0xC4), VS_F2_PIX_E_LSB = PAGE_ADDR(PAGE_CTRL, 0xC5),
  FREF_F1_S_MSB = PAGE_ADDR(PAGE_CTRL, 0xC6), FREF_F1_S_LSB = PAGE_ADDR(PAGE_CTRL, 0xC7), FREF_F2_S_MSB = PAGE_ADDR(PAGE_CTRL, 0xC8), FREF_F2_S_LSB = PAGE_ADDR(PAGE_CTRL, 0xC9),
  FDW_S_MSB = PAGE_ADDR(PAGE_CTRL, 0xCA), FDW_S_LSB = PAGE_ADDR(PAGE_CTRL, 0xCB), FDW_E_MSB = PAGE_ADDR(PAGE_CTRL, 0xCC), FDW_E_LSB = PAGE_ADDR(PAGE_CTRL, 0xCD),
  MEASLIN_MSB = PAGE_ADDR(PAGE_CTRL, 0xCE), MEASLIN_LSB = PAGE_ADDR(PAGE_CTRL, 0xCF), MEASPIX_MSB = PAGE_ADDR(PAGE_CTRL, 0xD0), MEASPIX_LSB = PAGE_ADDR(PAGE_CTRL, 0xD1),
  ASD_MEASLIN_MSB = PAGE_ADDR(PAGE_CTRL, 0xD2), BLK_GY_MSB = PAGE_ADDR(PAGE_CTRL, 0xDA), BLK_GY_LSB = PAGE_ADDR(PAGE_CTRL, 0xDB), BLK_BU_MSB = PAGE_ADDR(PAGE_CTRL, 0xDC),
  BLK_BU_LSB = PAGE_ADDR(PAGE_CTRL, 0xDD), BLK_RV_MSB = PAGE_ADDR(PAGE_CTRL, 0xDE), BLK_RV_LSB = PAGE_ADDR(PAGE_CTRL, 0xDF), FILTERS_CTRL = PAGE_ADDR(PAGE_CTRL, 0xE0),
  C_CEIL_MSB = PAGE_ADDR(PAGE_CTRL, 0xE1), C_CEIL_LSB = PAGE_ADDR(PAGE_CTRL, 0xE2), C_FLOOR_MSB = PAGE_ADDR(PAGE_CTRL, 0xE3), C_FLOOR_LSB = PAGE_ADDR(PAGE_CTRL, 0xE4),
  Y_CEIL_MSB = PAGE_ADDR(PAGE_CTRL, 0xE5), Y_CEIL_LSB = PAGE_ADDR(PAGE_CTRL, 0xE6), Y_FLOOR_MSB = PAGE_ADDR(PAGE_CTRL, 0xE7), Y_FLOOR_LSB = PAGE_ADDR(PAGE_CTRL, 0xE8),
  DITHERING_CTRL = PAGE_ADDR(PAGE_CTRL, 0xE9), OF_CTRL = PAGE_ADDR(PAGE_CTRL, 0xEA), CLKOUT_CTRL = PAGE_ADDR(PAGE_CTRL, 0xEB), HS_HREF_SEL = PAGE_ADDR(PAGE_CTRL, 0xEC),
  VS_VREF_SEL = PAGE_ADDR(PAGE_CTRL, 0xED), DE_FREF_SEL = PAGE_ADDR(PAGE_CTRL, 0xEE), VP35_32_CTRL = PAGE_ADDR(PAGE_CTRL, 0xEF), VP31_28_CTRL = PAGE_ADDR(PAGE_CTRL, 0xF0),
  VP27_24_CTRL = PAGE_ADDR(PAGE_CTRL, 0xF1), VP23_20_CTRL = PAGE_ADDR(PAGE_CTRL, 0xF2), VP19_16_CTRL = PAGE_ADDR(PAGE_CTRL, 0xF3), VP15_12_CTRL = PAGE_ADDR(PAGE_CTRL, 0xF4),
  VP11_8_CTRL = PAGE_ADDR(PAGE_CTRL, 0xF5), VP7_4_CTRL = PAGE_ADDR(PAGE_CTRL, 0xF6), VP3_0_CTRL = PAGE_ADDR(PAGE_CTRL, 0xF7), EMTP_CTRL = PAGE_ADDR(PAGE_CTRL, 0xFA),
  EMTP_ADDRESS = PAGE_ADDR(PAGE_CTRL, 0xFB), CMTP_CTRL = PAGE_ADDR(PAGE_CTRL, 0xFC), CMTP_ADDRESS = PAGE_ADDR(PAGE_CTRL, 0xFD), ECC_CHECK = PAGE_ADDR(PAGE_CTRL, 0xFE),
  HDMI_FLAGS = PAGE_ADDR(PAGE_HDMI, 0x00), DEEP_COLOR_MODE = PAGE_ADDR(PAGE_HDMI, 0x01), ERR_FR_MSB = PAGE_ADDR(PAGE_HDMI, 0x02), ERR_FR_LSB = PAGE_ADDR(PAGE_HDMI, 0x03),
  FR_ERR_MSB = PAGE_ADDR(PAGE_HDMI, 0x04), FR_ERR_LSB = PAGE_ADDR(PAGE_HDMI, 0x05), AUDIO_FLAGS = PAGE_ADDR(PAGE_HDMI, 0x08), AUDIO_FREQ = PAGE_ADDR(PAGE_HDMI, 0x09),
  ACRP_CTS_MSB = PAGE_ADDR(PAGE_HDMI, 0x0A), ACRP_CTS_ISB = PAGE_ADDR(PAGE_HDMI, 0x0B), ACRP_CTS_LSB = PAGE_ADDR(PAGE_HDMI, 0x0C), ACRP_N_MSB = PAGE_ADDR(PAGE_HDMI, 0x0D),
  ACRP_N_ISB = PAGE_ADDR(PAGE_HDMI, 0x0E), ACRP_N_LSB = PAGE_ADDR(PAGE_HDMI, 0x0F), CH_STAT_BYTE0 = PAGE_ADDR(PAGE_HDMI, 0x10), CH_STAT_BYTE1 = PAGE_ADDR(PAGE_HDMI, 0x11),
  CH_STAT_BYTE3 = PAGE_ADDR(PAGE_HDMI, 0x12), CH_STAT_BYTE4 = PAGE_ADDR(PAGE_HDMI, 0x13), CH_STAT_BYTE2_AP0_L = PAGE_ADDR(PAGE_HDMI, 0x14), CH_STAT_BYTE2_AP0_R = PAGE_ADDR(PAGE_HDMI, 0x15),
  CH_STAT_BYTE2_AP1_L = PAGE_ADDR(PAGE_HDMI, 0x16), CH_STAT_BYTE2_AP1_R = PAGE_ADDR(PAGE_HDMI, 0x17), CH_STAT_BYTE2_AP2_L = PAGE_ADDR(PAGE_HDMI, 0x18), CH_STAT_BYTE2_AP2_R = PAGE_ADDR(PAGE_HDMI, 0x19),
  CH_STAT_BYTE2_AP3_L = PAGE_ADDR(PAGE_HDMI, 0x1A), CH_STAT_BYTE2_AP3_R = PAGE_ADDR(PAGE_HDMI, 0x1B), GCP_PACKET_TYPE = PAGE_ADDR(PAGE_HDMI, 0x21), GCP_HEADER1 = PAGE_ADDR(PAGE_HDMI, 0x22),
  GCP_HEADER2 = PAGE_ADDR(PAGE_HDMI, 0x23), GCP_BYTE0 = PAGE_ADDR(PAGE_HDMI, 0x24), GCP_BYTE1 = PAGE_ADDR(PAGE_HDMI, 0x25), GCP_BYTE2 = PAGE_ADDR(PAGE_HDMI, 0x26),
  GCP_BYTE3 = PAGE_ADDR(PAGE_HDMI, 0x27), GCP_BYTE4 = PAGE_ADDR(PAGE_HDMI, 0x28), GCP_BYTE5 = PAGE_ADDR(PAGE_HDMI, 0x29), GCP_BYTE6 = PAGE_ADDR(PAGE_HDMI, 0x2A),
  ACP_UPDATE = PAGE_ADDR(PAGE_HDMI, 0x40), ACP_PACKET_TYPE = PAGE_ADDR(PAGE_HDMI, 0x41), ACP_TYPE = PAGE_ADDR(PAGE_HDMI, 0x42), ACP_RSVD = PAGE_ADDR(PAGE_HDMI, 0x43),
  ACP_BYTE0 = PAGE_ADDR(PAGE_HDMI, 0x44), ACP_BYTE1 = PAGE_ADDR(PAGE_HDMI, 0x45), ACP_BYTE2 = PAGE_ADDR(PAGE_HDMI, 0x46), ACP_BYTE3 = PAGE_ADDR(PAGE_HDMI, 0x47),
  ACP_BYTE4 = PAGE_ADDR(PAGE_HDMI, 0x48), ACP_BYTE5 = PAGE_ADDR(PAGE_HDMI, 0x49), ACP_BYTE6 = PAGE_ADDR(PAGE_HDMI, 0x4A), ACP_BYTE7 = PAGE_ADDR(PAGE_HDMI, 0x4B),
  ACP_BYTE8 = PAGE_ADDR(PAGE_HDMI, 0x4C), ACP_BYTE9 = PAGE_ADDR(PAGE_HDMI, 0x4D), ACP_BYTE10 = PAGE_ADDR(PAGE_HDMI, 0x4E), ACP_BYTE11 = PAGE_ADDR(PAGE_HDMI, 0x4F),
  ACP_BYTE12 = PAGE_ADDR(PAGE_HDMI, 0x50), ACP_BYTE13 = PAGE_ADDR(PAGE_HDMI, 0x51), ACP_BYTE14 = PAGE_ADDR(PAGE_HDMI, 0x52), ACP_BYTE15 = PAGE_ADDR(PAGE_HDMI, 0x53),
  ISRC1_PACKET_TYPE = PAGE_ADDR(PAGE_HDMI, 0x61), ISRC1_CTRL = PAGE_ADDR(PAGE_HDMI, 0x62), ISRC1_RSVD = PAGE_ADDR(PAGE_HDMI, 0x63), UPC_EAN_ISRC0 = PAGE_ADDR(PAGE_HDMI, 0x64),
  UPC_EAN_ISRC1 = PAGE_ADDR(PAGE_HDMI, 0x65), UPC_EAN_ISRC2 = PAGE_ADDR(PAGE_HDMI, 0x66), UPC_EAN_ISRC3 = PAGE_ADDR(PAGE_HDMI, 0x67), UPC_EAN_ISRC4 = PAGE_ADDR(PAGE_HDMI, 0x68),
  UPC_EAN_ISRC5 = PAGE_ADDR(PAGE_HDMI, 0x69), UPC_EAN_ISRC6 = PAGE_ADDR(PAGE_HDMI, 0x6A), UPC_EAN_ISRC7 = PAGE_ADDR(PAGE_HDMI, 0x6B), UPC_EAN_ISRC8 = PAGE_ADDR(PAGE_HDMI, 0x6C),
  UPC_EAN_ISRC9 = PAGE_ADDR(PAGE_HDMI, 0x6D), UPC_EAN_ISRC10 = PAGE_ADDR(PAGE_HDMI, 0x6E), UPC_EAN_ISRC11 = PAGE_ADDR(PAGE_HDMI, 0x6F), UPC_EAN_ISRC12 = PAGE_ADDR(PAGE_HDMI, 0x70),
  UPC_EAN_ISRC13 = PAGE_ADDR(PAGE_HDMI, 0x71), UPC_EAN_ISRC14 = PAGE_ADDR(PAGE_HDMI, 0x72), UPC_EAN_ISRC15 = PAGE_ADDR(PAGE_HDMI, 0x73), ISRC2_PACKET_TYPE = PAGE_ADDR(PAGE_HDMI, 0x81),
  ISRC2_RSVD1 = PAGE_ADDR(PAGE_HDMI, 0x82), ISRC2_RSVD2 = PAGE_ADDR(PAGE_HDMI, 0x83), UPC_EAN_ISRC16 = PAGE_ADDR(PAGE_HDMI, 0x84), UPC_EAN_ISRC17 = PAGE_ADDR(PAGE_HDMI, 0x85),
  UPC_EAN_ISRC18 = PAGE_ADDR(PAGE_HDMI, 0x86), UPC_EAN_ISRC19 = PAGE_ADDR(PAGE_HDMI, 0x87), UPC_EAN_ISRC20 = PAGE_ADDR(PAGE_HDMI, 0x88), UPC_EAN_ISRC21 = PAGE_ADDR(PAGE_HDMI, 0x89),
  UPC_EAN_ISRC22 = PAGE_ADDR(PAGE_HDMI, 0x8A), UPC_EAN_ISRC23 = PAGE_ADDR(PAGE_HDMI, 0x8B), UPC_EAN_ISRC24 = PAGE_ADDR(PAGE_HDMI, 0x8C), UPC_EAN_ISRC25 = PAGE_ADDR(PAGE_HDMI, 0x8D),
  UPC_EAN_ISRC26 = PAGE_ADDR(PAGE_HDMI, 0x8E), UPC_EAN_ISRC27 = PAGE_ADDR(PAGE_HDMI, 0x8F), UPC_EAN_ISRC28 = PAGE_ADDR(PAGE_HDMI, 0x90), UPC_EAN_ISRC29 = PAGE_ADDR(PAGE_HDMI, 0x91),
  UPC_EAN_ISRC30 = PAGE_ADDR(PAGE_HDMI, 0x92), UPC_EAN_ISRC31 = PAGE_ADDR(PAGE_HDMI, 0x93), GBD_UPDATE = PAGE_ADDR(PAGE_HDMI, 0xA0), GBD_PACKET_TYPE = PAGE_ADDR(PAGE_HDMI, 0xA1),
  GBD_HEADER1 = PAGE_ADDR(PAGE_HDMI, 0xA2), GBD_HEADER2 = PAGE_ADDR(PAGE_HDMI, 0xA3), GBD_BYTE0 = PAGE_ADDR(PAGE_HDMI, 0xA4), GBD_BYTE1 = PAGE_ADDR(PAGE_HDMI, 0xA5),
  GBD_BYTE2 = PAGE_ADDR(PAGE_HDMI, 0xA6), GBD_BYTE3 = PAGE_ADDR(PAGE_HDMI, 0xA7), GBD_BYTE4 = PAGE_ADDR(PAGE_HDMI, 0xA8), GBD_BYTE5 = PAGE_ADDR(PAGE_HDMI, 0xA9),
  GBD_BYTE6 = PAGE_ADDR(PAGE_HDMI, 0xAA), GBD_BYTE7 = PAGE_ADDR(PAGE_HDMI, 0xAB), GBD_BYTE8 = PAGE_ADDR(PAGE_HDMI, 0xAC), GBD_BYTE9 = PAGE_ADDR(PAGE_HDMI, 0xAD),
  GBD_BYTE10 = PAGE_ADDR(PAGE_HDMI, 0xAE), GBD_BYTE11 = PAGE_ADDR(PAGE_HDMI, 0xAF), GBD_BYTE12 = PAGE_ADDR(PAGE_HDMI, 0xB0), GBD_BYTE13 = PAGE_ADDR(PAGE_HDMI, 0xB1),
  GBD_BYTE14 = PAGE_ADDR(PAGE_HDMI, 0xB2), GBD_BYTE15 = PAGE_ADDR(PAGE_HDMI, 0xB3), GBD_BYTE16 = PAGE_ADDR(PAGE_HDMI, 0xB4), GBD_BYTE17 = PAGE_ADDR(PAGE_HDMI, 0xB5),
  GBD_BYTE18 = PAGE_ADDR(PAGE_HDMI, 0xB6), GBD_BYTE19 = PAGE_ADDR(PAGE_HDMI, 0xB7), GBD_BYTE20 = PAGE_ADDR(PAGE_HDMI, 0xB8), GBD_BYTE21 = PAGE_ADDR(PAGE_HDMI, 0xB9),
  GBD_BYTE22 = PAGE_ADDR(PAGE_HDMI, 0xBA), GBD_BYTE23 = PAGE_ADDR(PAGE_HDMI, 0xBB), GBD_BYTE24 = PAGE_ADDR(PAGE_HDMI, 0xBC), GBD_BYTE25 = PAGE_ADDR(PAGE_HDMI, 0xBD),
  GBD_BYTE26 = PAGE_ADDR(PAGE_HDMI, 0xBE), GBD_BYTE27 = PAGE_ADDR(PAGE_HDMI, 0xBF), HDCP_RI_MSB = PAGE_ADDR(PAGE_HDMI, 0xE0), HDCP_RI_LSB = PAGE_ADDR(PAGE_HDMI, 0xE1),
  HDCP_PJ = PAGE_ADDR(PAGE_HDMI, 0xE2), HDCP_AKSV4 = PAGE_ADDR(PAGE_HDMI, 0xE3), HDCP_AKSV3 = PAGE_ADDR(PAGE_HDMI, 0xE4), HDCP_AKSV2 = PAGE_ADDR(PAGE_HDMI, 0xE5),
  HDCP_AKSV1 = PAGE_ADDR(PAGE_HDMI, 0xE6), HDCP_AKSV0 = PAGE_ADDR(PAGE_HDMI, 0xE7), HDCP_AN7 = PAGE_ADDR(PAGE_HDMI, 0xE8), HDCP_AN6 = PAGE_ADDR(PAGE_HDMI, 0xE9),
  HDCP_AN5 = PAGE_ADDR(PAGE_HDMI, 0xEA), HDCP_AN4 = PAGE_ADDR(PAGE_HDMI, 0xEB), HDCP_AN3 = PAGE_ADDR(PAGE_HDMI, 0xEC), HDCP_AN2 = PAGE_ADDR(PAGE_HDMI, 0xED),
  HDCP_AN1 = PAGE_ADDR(PAGE_HDMI, 0xEE), HDCP_AN0 = PAGE_ADDR(PAGE_HDMI, 0xEF), HDCP_AINFO = PAGE_ADDR(PAGE_HDMI, 0xF0), HDCP_FSM_STATE = PAGE_ADDR(PAGE_HDMI, 0xF1),
  VS_IF_HDMI_UPDATE = PAGE_ADDR(PAGE_AVI, 0x00), VS_IF_HDMI_TYPE = PAGE_ADDR(PAGE_AVI, 0x01), VS_IF_HDMI_VERSION = PAGE_ADDR(PAGE_AVI, 0x02), VS_IF_HDMI_LENGTH = PAGE_ADDR(PAGE_AVI, 0x03),
  VS_IF_HDMI_CHECKSUM = PAGE_ADDR(PAGE_AVI, 0x04), VS_IF_HDMI_BYTE1 = PAGE_ADDR(PAGE_AVI, 0x05), VS_IF_HDMI_BYTE27 = PAGE_ADDR(PAGE_AVI, 0x1F), VS_IF_OTHER_BK1_UPDATE = PAGE_ADDR(PAGE_AVI, 0x20),
  VS_IF_OTHER_BK1_TYPE = PAGE_ADDR(PAGE_AVI, 0x21), VS_IF_OTHER_BK1_VERSION = PAGE_ADDR(PAGE_AVI, 0x22), VS_IF_OTHER_BK1_LENGTH = PAGE_ADDR(PAGE_AVI, 0x23), VS_IF_OTHER_BK1_CHECKSUM = PAGE_ADDR(PAGE_AVI, 0x24),
  VS_IF_OTHER_BK1_BYTE1 = PAGE_ADDR(PAGE_AVI, 0x25), VS_IF_OTHER_BK1_BYTE27 = PAGE_ADDR(PAGE_AVI, 0x3F), VS_IF_OTHER_BK2_UPDATE = PAGE_ADDR(PAGE_AVI, 0x40), VS_IF_OTHER_BK2_TYPE = PAGE_ADDR(PAGE_AVI, 0x41),
  VS_IF_OTHER_BK2_VERSION = PAGE_ADDR(PAGE_AVI, 0x42), VS_IF_OTHER_BK2_LENGTH = PAGE_ADDR(PAGE_AVI, 0x43), VS_IF_OTHER_BK2_CHECKSUM = PAGE_ADDR(PAGE_AVI, 0x44), VS_IF_OTHER_BK2_BYTE1 = PAGE_ADDR(PAGE_AVI, 0x45),
  VS_IF_OTHER_BK2_BYTE27 = PAGE_ADDR(PAGE_AVI, 0x5F), AVI_IF_UPDATE = PAGE_ADDR(PAGE_AVI, 0x60), AVI_IF_TYPE = PAGE_ADDR(PAGE_AVI, 0x61), AVI_IF_VERSION = PAGE_ADDR(PAGE_AVI, 0x62),
  AVI_IF_LENGTH = PAGE_ADDR(PAGE_AVI, 0x63), AVI_IF_CHECKSUM = PAGE_ADDR(PAGE_AVI, 0x64), AVI_IF_BYTE1 = PAGE_ADDR(PAGE_AVI, 0x65), AVI_IF_BYTE13 = PAGE_ADDR(PAGE_AVI, 0x71),
  SPD_IF_UPDATE = PAGE_ADDR(PAGE_AVI, 0x80), SPD_IF_TYPE = PAGE_ADDR(PAGE_AVI, 0x81), SPD_IF_VERSION = PAGE_ADDR(PAGE_AVI, 0x82), SPD_IF_LENGTH = PAGE_ADDR(PAGE_AVI, 0x83),
  SPD_IF_CHECKSUM = PAGE_ADDR(PAGE_AVI, 0x84), SPD_IF_BYTE1 = PAGE_ADDR(PAGE_AVI, 0x85), SPD_IF_BYTE27 = PAGE_ADDR(PAGE_AVI, 0x9F), AUD_IF_UPDATE = PAGE_ADDR(PAGE_AVI, 0xA0),
  AUD_IF_TYPE = PAGE_ADDR(PAGE_AVI, 0xA1), AUD_IF_VERSION = PAGE_ADDR(PAGE_AVI, 0xA2), AUD_IF_LENGTH = PAGE_ADDR(PAGE_AVI, 0xA3), AUD_IF_CHECKSUM = PAGE_ADDR(PAGE_AVI, 0xA4),
  AUD_IF_BYTE1 = PAGE_ADDR(PAGE_AVI, 0xA5), AUD_IF_BYTE10 = PAGE_ADDR(PAGE_AVI, 0xAE), MPS_IF_UPDATE = PAGE_ADDR(PAGE_AVI, 0xC0), MPS_IF_TYPE = PAGE_ADDR(PAGE_AVI, 0xC1),
  MPS_IF_VERSION = PAGE_ADDR(PAGE_AVI, 0xC2), MPS_IF_LENGTH = PAGE_ADDR(PAGE_AVI, 0xC3), MPS_IF_CHECKSUM = PAGE_ADDR(PAGE_AVI, 0xC4), MPS_IF_BYTE1 = PAGE_ADDR(PAGE_AVI, 0xC5),
  MPS_IF_BYTE10 = PAGE_ADDR(PAGE_AVI, 0xCE), CHECKSUM_VS_IF_HDMI = PAGE_ADDR(PAGE_AVI, 0xE0), CHECKSUM_VS_IF_OTHER_BK1 = PAGE_ADDR(PAGE_AVI, 0xE1), CHECKSUM_VS_IF_OTHER_BK2 = PAGE_ADDR(PAGE_AVI, 0xE2),
  CHECKSUM_AVI_IF = PAGE_ADDR(PAGE_AVI, 0xE3), CHECKSUM_SPD_IF = PAGE_ADDR(PAGE_AVI, 0xE4), CHECKSUM_AUD_IF = PAGE_ADDR(PAGE_AVI, 0xE5), CHECKSUM_MPS_IF = PAGE_ADDR(PAGE_AVI, 0xE6),
  CLK_CFG = PAGE_ADDR(PAGE_TMDSA, 0x00), CLK_OUT_CFG = PAGE_ADDR(PAGE_TMDSA, 0x01), CFG1 = PAGE_ADDR(PAGE_TMDSA, 0x02), CFG2 = PAGE_ADDR(PAGE_TMDSA, 0x03),
  PHS_CONF = PAGE_ADDR(PAGE_TMDSA, 0x05), PHS_AVERAGINGK = PAGE_ADDR(PAGE_TMDSA, 0x06), PHS_CH0_OVRD = PAGE_ADDR(PAGE_TMDSA, 0x07), PHS_CH1_OVRD = PAGE_ADDR(PAGE_TMDSA, 0x08),
  PHS_CH2_OVRD = PAGE_ADDR(PAGE_TMDSA, 0x09), PHS_CH0_USED = PAGE_ADDR(PAGE_TMDSA, 0x0A), PHS_CH1_USED = PAGE_ADDR(PAGE_TMDSA, 0x0B), PHS_CH2_USED = PAGE_ADDR(PAGE_TMDSA, 0x0C),
  WDL_CFG = PAGE_ADDR(PAGE_TMDSA, 0x10), WDL_FROZEN = PAGE_ADDR(PAGE_TMDSA, 0x11), DELOCK_DELAY = PAGE_ADDR(PAGE_TMDSA, 0x12), SWAP_PN = PAGE_ADDR(PAGE_TMDSA, 0x13),
  OFFSET_CH0_SELPHS = PAGE_ADDR(PAGE_TMDSA, 0x18), OFFSET_CH1_SELPHS = PAGE_ADDR(PAGE_TMDSA, 0x19), OFFSET_CH2_SELPHS = PAGE_ADDR(PAGE_TMDSA, 0x1A), OFFSET_OSM_OVR = PAGE_ADDR(PAGE_TMDSA, 0x1B),
  OFFSET_CH0_OVRD = PAGE_ADDR(PAGE_TMDSA, 0x1C), OFFSET_CH1_OVRD = PAGE_ADDR(PAGE_TMDSA, 0x1D), OFFSET_CH2_OVRD = PAGE_ADDR(PAGE_TMDSA, 0x1E), OFFSET_CH0 = PAGE_ADDR(PAGE_TMDSA, 0x1F),
  OFFSET_CH1 = PAGE_ADDR(PAGE_TMDSA, 0x20), OFFSET_CH2 = PAGE_ADDR(PAGE_TMDSA, 0x21), SW_OFFSETCAL_EN = PAGE_ADDR(PAGE_TMDSA, 0x22), OFFSETCAL_RES = PAGE_ADDR(PAGE_TMDSA, 0x23),
  GAIN_CFG1 = PAGE_ADDR(PAGE_TMDSA, 0x28), GAIN_CFG2 = PAGE_ADDR(PAGE_TMDSA, 0x29), GAIN_CFG3 = PAGE_ADDR(PAGE_TMDSA, 0x2A), GAIN_CH0 = PAGE_ADDR(PAGE_TMDSA, 0x2B),
  GAIN_CH1 = PAGE_ADDR(PAGE_TMDSA, 0x2C), GAIN_CH2 = PAGE_ADDR(PAGE_TMDSA, 0x2D), ACTIVITY = PAGE_ADDR(PAGE_TMDSA, 0x2E), GAIN_TEMPKICK = PAGE_ADDR(PAGE_TMDSA, 0x2F),
  GAIN_OVR_EN = PAGE_ADDR(PAGE_TMDSA, 0x30), GAIN_CH0_OVRD = PAGE_ADDR(PAGE_TMDSA, 0x31), GAIN_CH1_OVRD = PAGE_ADDR(PAGE_TMDSA, 0x32), GAIN_CH2_OVRD = PAGE_ADDR(PAGE_TMDSA, 0x33),
  SW_GAINCAL_EN = PAGE_ADDR(PAGE_TMDSA, 0x34), GAINCAL_RES = PAGE_ADDR(PAGE_TMDSA, 0x35), PLL_RSV = PAGE_ADDR(PAGE_TMDSA, 0x38), PLL_PFD_OVR = PAGE_ADDR(PAGE_TMDSA, 0x39),
  PLL_LOCKFILTER = PAGE_ADDR(PAGE_TMDSA, 0x3A), PLL_IPCP = PAGE_ADDR(PAGE_TMDSA, 0x3B), PLL_TMDS_CTRL = PAGE_ADDR(PAGE_TMDSA, 0x3C), PLL_SEL_PHS = PAGE_ADDR(PAGE_TMDSA, 0x3D),
  PLL_STATUS = PAGE_ADDR(PAGE_TMDSA, 0x3E), ASU_STATE_CTRL = PAGE_ADDR(PAGE_TMDSA, 0x40), ASU_STATE_READ = PAGE_ADDR(PAGE_TMDSA, 0x41), ASU_EQ_CALTIME = PAGE_ADDR(PAGE_TMDSA, 0x42),
  ASU_NO_WAIT_ACT = PAGE_ADDR(PAGE_TMDSA, 0x43), ASU_USE_PLL = PAGE_ADDR(PAGE_TMDSA, 0x44), EQ_REFTIM_SLOWx4 = PAGE_ADDR(PAGE_TMDSA, 0x45), EQ_REFTIM_MSB = PAGE_ADDR(PAGE_TMDSA, 0x46),
  EQ_REFTIM_LSB = PAGE_ADDR(PAGE_TMDSA, 0x47), MODE_TX_EN = PAGE_ADDR(PAGE_TMDSA, 0x5A), FREEZE_EN = PAGE_ADDR(PAGE_TMDSA, 0x5B), MODE_DIG_EN = PAGE_ADDR(PAGE_TMDSA, 0x5C),
  TRM_INV_CMP = PAGE_ADDR(PAGE_TMDSA, 0x60), TRM_OVR = PAGE_ADDR(PAGE_TMDSA, 0x61), TRM_SW_CAL_EN = PAGE_ADDR(PAGE_TMDSA, 0x62), TRM_STATUS = PAGE_ADDR(PAGE_TMDSA, 0x63),
  CAL_RES_SEL_CH = PAGE_ADDR(PAGE_TMDSA, 0x68), RESULT_OFFSETCNT_MSB = PAGE_ADDR(PAGE_TMDSA, 0x69), RESULT_OFFSETCNT_LSB = PAGE_ADDR(PAGE_TMDSA, 0x6A), RESULT_STDDEV_MSB = PAGE_ADDR(PAGE_TMDSA, 0x6B),
  RESULT_STDDEV_LSB = PAGE_ADDR(PAGE_TMDSA, 0x6C), RESULT_EDGECOUNT_PH0_MSB = PAGE_ADDR(PAGE_TMDSA, 0x6D), RESULT_EDGECOUNT_PH0_LSB = PAGE_ADDR(PAGE_TMDSA, 0x6E), RESULT_EDGECOUNT_PH1_MSB = PAGE_ADDR(PAGE_TMDSA, 0x6F),
  RESULT_EDGECOUNT_PH1_LSB = PAGE_ADDR(PAGE_TMDSA, 0x70), RESULT_EDGECOUNT_PH2_MSB = PAGE_ADDR(PAGE_TMDSA, 0x71), RESULT_EDGECOUNT_PH2_LSB = PAGE_ADDR(PAGE_TMDSA, 0x72), RESULT_EDGECOUNT_PH3_MSB = PAGE_ADDR(PAGE_TMDSA, 0x73),
  RESULT_EDGECOUNT_PH3_LSB = PAGE_ADDR(PAGE_TMDSA, 0x74), RESULT_EDGECOUNT_PH4_MSB = PAGE_ADDR(PAGE_TMDSA, 0x75), RESULT_EDGECOUNT_PH4_LSB = PAGE_ADDR(PAGE_TMDSA, 0x76), RESULT_EDGECOUNT_PH5_MSB = PAGE_ADDR(PAGE_TMDSA, 0x77),
  RESULT_EDGECOUNT_PH5_LSB = PAGE_ADDR(PAGE_TMDSA, 0x78), RESULT_HISTOGRAM0_MSB = PAGE_ADDR(PAGE_TMDSA, 0x79), RESULT_HISTOGRAM0_LSB = PAGE_ADDR(PAGE_TMDSA, 0x7A), RESULT_HISTOGRAM1_MSB = PAGE_ADDR(PAGE_TMDSA, 0x7B),
  RESULT_HISTOGRAM1_LSB = PAGE_ADDR(PAGE_TMDSA, 0x7C), RESULT_HISTOGRAM2_MSB = PAGE_ADDR(PAGE_TMDSA, 0x7D), RESULT_HISTOGRAM2_LSB = PAGE_ADDR(PAGE_TMDSA, 0x7E), RESULT_HISTOGRAM3_MSB = PAGE_ADDR(PAGE_TMDSA, 0x7F),
  RESULT_HISTOGRAM3_LSB = PAGE_ADDR(PAGE_TMDSA, 0x80), RESULT_HISTOGRAM4_MSB = PAGE_ADDR(PAGE_TMDSA, 0x81), RESULT_HISTOGRAM4_LSB = PAGE_ADDR(PAGE_TMDSA, 0x82), RESULT_HISTOGRAM5_MSB = PAGE_ADDR(PAGE_TMDSA, 0x83),
  RESULT_HISTOGRAM5_LSB = PAGE_ADDR(PAGE_TMDSA, 0x84), RESULT_HISTOGRAM6_MSB = PAGE_ADDR(PAGE_TMDSA, 0x85), RESULT_HISTOGRAM6_LSB = PAGE_ADDR(PAGE_TMDSA, 0x86), RESULT_HISTOGRAM7_MSB = PAGE_ADDR(PAGE_TMDSA, 0x87),
  RESULT_HISTOGRAM7_LSB = PAGE_ADDR(PAGE_TMDSA, 0x88), DEBUG_TYPE = PAGE_ADDR(PAGE_TMDSA, 0x90), DEBUG_CTRL = PAGE_ADDR(PAGE_TMDSA, 0x91), DEBUG_NB_WORD = PAGE_ADDR(PAGE_TMDSA, 0x92),
  DEBUG_TMDS_CLK_MSB = PAGE_ADDR(PAGE_TMDSA, 0x93), DEBUG_TMDS_CLK_LSB = PAGE_ADDR(PAGE_TMDSA, 0x94), DEBUG_TMDS_WORD_MSB = PAGE_ADDR(PAGE_TMDSA, 0x95), DEBUG_TMDS_LSB_MSB = PAGE_ADDR(PAGE_TMDSA, 0x96),
  DEBUG_MUX_SW_ENA = PAGE_ADDR(PAGE_TMDSA, 0x97), PON_OVR_EN = PAGE_ADDR(PAGE_TMDSA, 0xA0), PON_CBIAS = PAGE_ADDR(PAGE_TMDSA, 0xA1), PON_RESCAL = PAGE_ADDR(PAGE_TMDSA, 0xA2),
  PON_RES = PAGE_ADDR(PAGE_TMDSA, 0xA3), PON_CLK = PAGE_ADDR(PAGE_TMDSA, 0xA4), PON_PLL = PAGE_ADDR(PAGE_TMDSA, 0xA5), PON_EQ = PAGE_ADDR(PAGE_TMDSA, 0xA6),
  PON_DES = PAGE_ADDR(PAGE_TMDSA, 0xA7), PON_OUT = PAGE_ADDR(PAGE_TMDSA, 0xA8), PON_MUX = PAGE_ADDR(PAGE_TMDSA, 0xA9), EQ_CALIBRATION = PAGE_ADDR(PAGE_TMDSA, 0xAA),
  BIST_CTRL1 = PAGE_ADDR(PAGE_TMDSA, 0xB0), BIST_CTRL2 = PAGE_ADDR(PAGE_TMDSA, 0xB1), BIST_CTRL3 = PAGE_ADDR(PAGE_TMDSA, 0xB2), BIST_TCB_REG_TIMOUT = PAGE_ADDR(PAGE_TMDSA, 0xB3),
  BIST_CORREL_RESULT_MSB = PAGE_ADDR(PAGE_TMDSA, 0xB4), BIST_CORREL_RESULT_LSB = PAGE_ADDR(PAGE_TMDSA, 0xB5), BIST_CORREL_LENGTH3 = PAGE_ADDR(PAGE_TMDSA, 0xB6), BIST_CORREL_LENGTH2 = PAGE_ADDR(PAGE_TMDSA, 0xB7),
  BIST_CORREL_LENGTH1 = PAGE_ADDR(PAGE_TMDSA, 0xB8), BIST_CORREL_LENGTH0 = PAGE_ADDR(PAGE_TMDSA, 0xB9), BIST_GAIN_CH0 = PAGE_ADDR(PAGE_TMDSA, 0xBA), BIST_GAIN_CH1 = PAGE_ADDR(PAGE_TMDSA, 0xBB),
  BIST_GAIN_CH2 = PAGE_ADDR(PAGE_TMDSA, 0xBC), BIST_STATUS = PAGE_ADDR(PAGE_TMDSA, 0xBD), IRQ_SET_TOP = PAGE_ADDR(PAGE_TMDSA, 0xC0), IRQ_SET_SUS = PAGE_ADDR(PAGE_TMDSA, 0xC1),
  IRQ_SET_DDC = PAGE_ADDR(PAGE_TMDSA, 0xC2), IRQ_SET_RATE = PAGE_ADDR(PAGE_TMDSA, 0xC3), IRQ_SET_MODE = PAGE_ADDR(PAGE_TMDSA, 0xC4), IRQ_SET_INFO = PAGE_ADDR(PAGE_TMDSA, 0xC5),
  IRQ_SET_AUDIO = PAGE_ADDR(PAGE_TMDSA, 0xC6), IRQ_SET_HDCP = PAGE_ADDR(PAGE_TMDSA, 0xC7), IRQ_SET_AFE = PAGE_ADDR(PAGE_TMDSA, 0xC8), AUDIO_LAYOUT = PAGE_ADDR(PAGE_TMDSA, 0xD0),
  SEL_RD_VAL = PAGE_ADDR(PAGE_TMDSA, 0xD1), FRAME_START_WIDTH = PAGE_ADDR(PAGE_TMDSA, 0xD2), DELTA_WR_RD_PNTR = PAGE_ADDR(PAGE_TMDSA, 0xD3), BCH_DECODER = PAGE_ADDR(PAGE_TMDSA, 0xD4),
  TX_BUFFER_CFG = PAGE_ADDR(PAGE_TMDSA, 0xF6), MODE_RECOVER_CFG1 = PAGE_ADDR(PAGE_TMDSA, 0xF8), MODE_RECOVER_CFG2 = PAGE_ADDR(PAGE_TMDSA, 0xF9), MODE_RECOVER_STATUS = PAGE_ADDR(PAGE_TMDSA, 0xFA),
  DEEP_COLOR_CTRL = PAGE_ADDR(PAGE_TMDSB, 0x00), DEEP_COLOR_MAN = PAGE_ADDR(PAGE_TMDSB, 0x01), DEEP_COLOR_GCP = PAGE_ADDR(PAGE_TMDSB, 0x02), IVS_SEL = PAGE_ADDR(PAGE_TMDSB, 0x03),
  CGU_DEBUG_INV = PAGE_ADDR(PAGE_TMDSB, 0x04), CGU_DEBUG_SEL = PAGE_ADDR(PAGE_TMDSB, 0x05), X_OUTPUTS = PAGE_ADDR(PAGE_TMDSB, 0x06), VP_DEBUG = PAGE_ADDR(PAGE_TMDSB, 0x07),
  DEEP_COLOR_CLK_CTRL = PAGE_ADDR(PAGE_TMDSB, 0x08), DC_PAT0_MSB = PAGE_ADDR(PAGE_TMDSB, 0x09), DC_PAT1_MSB = PAGE_ADDR(PAGE_TMDSB, 0x0A), DC_PAT2_MSB = PAGE_ADDR(PAGE_TMDSB, 0x0B),
  DC_PAT3_MSB = PAGE_ADDR(PAGE_TMDSB, 0x0C), DC_PAT4_MSB = PAGE_ADDR(PAGE_TMDSB, 0x0D), DC_PAT3210_LSB = PAGE_ADDR(PAGE_TMDSB, 0x0E), DEEP_COLOR_PAT_MAN = PAGE_ADDR(PAGE_TMDSB, 0x0F),
  HDCP_DDC_ADDR = PAGE_ADDR(PAGE_TMDSB, 0x10), HDCP_BKSV4 = PAGE_ADDR(PAGE_TMDSB, 0x11), HDCP_BKSV3 = PAGE_ADDR(PAGE_TMDSB, 0x12), HDCP_BKSV2 = PAGE_ADDR(PAGE_TMDSB, 0x13),
  HDCP_BKSV1 = PAGE_ADDR(PAGE_TMDSB, 0x14), HDCP_BKSV0 = PAGE_ADDR(PAGE_TMDSB, 0x15), HDCP_KIDX = PAGE_ADDR(PAGE_TMDSB, 0x16), HDCP_KEY6 = PAGE_ADDR(PAGE_TMDSB, 0x17),
  HDCP_KEY5 = PAGE_ADDR(PAGE_TMDSB, 0x18), HDCP_KEY4 = PAGE_ADDR(PAGE_TMDSB, 0x19), HDCP_KEY3 = PAGE_ADDR(PAGE_TMDSB, 0x1A), HDCP_KEY2 = PAGE_ADDR(PAGE_TMDSB, 0x1B),
  HDCP_KEY1 = PAGE_ADDR(PAGE_TMDSB, 0x1C), HDCP_KEY0 = PAGE_ADDR(PAGE_TMDSB, 0x1D), HMTP_T_RESET = PAGE_ADDR(PAGE_TMDSB, 0x60), HMTP_T_ADDRESS_SETUP = PAGE_ADDR(PAGE_TMDSB, 0x61),
  HMTP_T_ADDRESS_HOLD = PAGE_ADDR(PAGE_TMDSB, 0x62), HMTP_T_READ_ENABLE = PAGE_ADDR(PAGE_TMDSB, 0x63), HMTP_T_WRITE_ENABLE = PAGE_ADDR(PAGE_TMDSB, 0x64), HMTP_T_INITIALIZATION = PAGE_ADDR(PAGE_TMDSB, 0x65),
  HMTP_T_ERASE_PRG_PROGRESS = PAGE_ADDR(PAGE_TMDSB, 0x66), HMTP_T_DISCHARGE = PAGE_ADDR(PAGE_TMDSB, 0x67), HDCP_SRAM_REGS = PAGE_ADDR(PAGE_TMDSB, 0x68), HDCP_DMA_CONF = PAGE_ADDR(PAGE_TMDSB, 0x69),
  HMTP_ECC_REGISTERS = PAGE_ADDR(PAGE_TMDSB, 0x6A), HMTP_ERR_ADDR = PAGE_ADDR(PAGE_TMDSB, 0x6B), HDCP_MTP_TEST = PAGE_ADDR(PAGE_TMDSB, 0x6C), HMTP_PARAM = PAGE_ADDR(PAGE_TMDSB, 0x6D),
  HDCP_DE_CTRL = PAGE_ADDR(PAGE_TMDSB, 0x70), HDCP_EP_FILT_CTRL = PAGE_ADDR(PAGE_TMDSB, 0x71), HDCP_EP_REM_CTRL = PAGE_ADDR(PAGE_TMDSB, 0x72), HDCP_EP_READ = PAGE_ADDR(PAGE_TMDSB, 0x73),
  HDCP_PA_CTRL = PAGE_ADDR(PAGE_TMDSB, 0x74), HDCP_PA_READ = PAGE_ADDR(PAGE_TMDSB, 0x75), HDCP_MISC = PAGE_ADDR(PAGE_TMDSB, 0x76), HDMI_CTRL = PAGE_ADDR(PAGE_TMDSB, 0x77),
  HDMI_POL = PAGE_ADDR(PAGE_TMDSB, 0x78), HDCP_MODE_RECOVERY = PAGE_ADDR(PAGE_TMDSB, 0x79), HMTP_CTRL = PAGE_ADDR(PAGE_TMDSB, 0x7A), HMTP_ADDRESS = PAGE_ADDR(PAGE_TMDSB, 0x7B),
  EMTP_T_RESET = PAGE_ADDR(PAGE_TMDSB, 0x80), EMTP_T_ADDRESS_SETUP = PAGE_ADDR(PAGE_TMDSB, 0x81), EMTP_T_ADDRESS_HOLD = PAGE_ADDR(PAGE_TMDSB, 0x82), EMTP_T_READ_ENABLE = PAGE_ADDR(PAGE_TMDSB, 0x83),
  EMTP_T_WRITE_ENABLE = PAGE_ADDR(PAGE_TMDSB, 0x84), EMTP_T_INITIALIZATION = PAGE_ADDR(PAGE_TMDSB, 0x85), EMTP_T_ERASE_PRG_PROG = PAGE_ADDR(PAGE_TMDSB, 0x86), EMTP_T_DISCHARGE = PAGE_ADDR(PAGE_TMDSB, 0x87),
  DDC_HIDDEN0_REGISTER = PAGE_ADDR(PAGE_TMDSB, 0x90), DDC_HIDDEN1_REGISTER = PAGE_ADDR(PAGE_TMDSB, 0x91), DDC_DMA_CONF = PAGE_ADDR(PAGE_TMDSB, 0x92), EMTP_ECC_CONF = PAGE_ADDR(PAGE_TMDSB, 0x93),
  EMTP_ERR_ADDR = PAGE_ADDR(PAGE_TMDSB, 0x94), HDCP_ACK_TIMER = PAGE_ADDR(PAGE_TMDSB, 0x96), HDCP_NOACK_TIMER = PAGE_ADDR(PAGE_TMDSB, 0x97), EMTP_PARAM = PAGE_ADDR(PAGE_TMDSB, 0x98),
  DDC_MTP_VANALOG = PAGE_ADDR(PAGE_TMDSB, 0x99), DDC_MTP_TEST = PAGE_ADDR(PAGE_TMDSB, 0x9A), DDC_MST_CTRL = PAGE_ADDR(PAGE_TMDSB, 0xA0), DDC_MST_CLK_DIV = PAGE_ADDR(PAGE_TMDSB, 0xA1),
  DDC_MST_CLK_DIV_FOR_MST = PAGE_ADDR(PAGE_TMDSB, 0xA2), DDC_LINK_SEL = PAGE_ADDR(PAGE_TMDSB, 0xA3), DDC_STATUS = PAGE_ADDR(PAGE_TMDSB, 0xA4), CLOCK_CTRL = PAGE_ADDR(PAGE_TMDSB, 0xA5),
  MONITOR_OFFSET_CH0_AB = PAGE_ADDR(PAGE_TMDSB, 0xC0), MONITOR_OFFSET_CH1_AB = PAGE_ADDR(PAGE_TMDSB, 0xC1), MONITOR_OFFSET_CH2_AB = PAGE_ADDR(PAGE_TMDSB, 0xC2), MONITOR_GAIN_CH0_AB = PAGE_ADDR(PAGE_TMDSB, 0xC3),
  MONITOR_GAIN_CH1_AB = PAGE_ADDR(PAGE_TMDSB, 0xC4), MONITOR_GAIN_CH2_AB = PAGE_ADDR(PAGE_TMDSB, 0xC5), SUS_CTRL = PAGE_ADDR(PAGE_TMDSB, 0xC6), SUS_CTRL2 = PAGE_ADDR(PAGE_TMDSB, 0xC7),
  RESET_REFTIM_MSB = PAGE_ADDR(PAGE_TMDSB, 0xC8), RESET_REFTIM_LSB = PAGE_ADDR(PAGE_TMDSB, 0xC9), TIMER_RT = PAGE_ADDR(PAGE_TMDSB, 0xCA), TIMER_A_MSB = PAGE_ADDR(PAGE_TMDSB, 0xCB),
  TIMER_B_MSB = PAGE_ADDR(PAGE_TMDSB, 0xCC), TIMER_C_MSB = PAGE_ADDR(PAGE_TMDSB, 0xCD), TIMER_ABC_LSB = PAGE_ADDR(PAGE_TMDSB, 0xCE), TIMER_D = PAGE_ADDR(PAGE_TMDSB, 0xCF),
  SUS_SET_CAL0 = PAGE_ADDR(PAGE_TMDSB, 0xD0), SUS_SET_CAL1 = PAGE_ADDR(PAGE_TMDSB, 0xD1), SUS_SET_CAL2 = PAGE_ADDR(PAGE_TMDSB, 0xD2), SUS_SET_CAL3 = PAGE_ADDR(PAGE_TMDSB, 0xD3),
  SUS_SET_CAL4 = PAGE_ADDR(PAGE_TMDSB, 0xD4), SUS_SET_CAL5 = PAGE_ADDR(PAGE_TMDSB, 0xD5), SUS_SET_CAL6 = PAGE_ADDR(PAGE_TMDSB, 0xD6), SUS_SET_CAL7 = PAGE_ADDR(PAGE_TMDSB, 0xD7),
  SUS_SET_CAL8 = PAGE_ADDR(PAGE_TMDSB, 0xD8), SUS_SET_HDMI0 = PAGE_ADDR(PAGE_TMDSB, 0xD9), SUS_SET_HDMI1 = PAGE_ADDR(PAGE_TMDSB, 0xDA), SUS_SET_HDMI2 = PAGE_ADDR(PAGE_TMDSB, 0xDB),
  SUS_SET_HDMI3 = PAGE_ADDR(PAGE_TMDSB, 0xDC), SUS_SET_HDMI4 = PAGE_ADDR(PAGE_TMDSB, 0xDD), SUS_SET_HDMI5 = PAGE_ADDR(PAGE_TMDSB, 0xDE), SUS_SET_HDMI6 = PAGE_ADDR(PAGE_TMDSB, 0xDF),
  SUS_SET_HDMI7 = PAGE_ADDR(PAGE_TMDSB, 0xE0), SUS_SET_RGB0 = PAGE_ADDR(PAGE_TMDSB, 0xE1), SUS_SET_RGB1 = PAGE_ADDR(PAGE_TMDSB, 0xE2), SUS_SET_RGB2 = PAGE_ADDR(PAGE_TMDSB, 0xE3),
  SUS_SET_RGB3 = PAGE_ADDR(PAGE_TMDSB, 0xE4), SUS_SET_RGB4 = PAGE_ADDR(PAGE_TMDSB, 0xE5), MAN_SUS_CAL_SEL = PAGE_ADDR(PAGE_TMDSB, 0xE6), MAN_CAL_SET = PAGE_ADDR(PAGE_TMDSB, 0xE7),
  MAN_SUS_HDMI_SEL = PAGE_ADDR(PAGE_TMDSB, 0xE8), MAN_HDMI_SET = PAGE_ADDR(PAGE_TMDSB, 0xE9), MAN_SUS_RGB_SEL = PAGE_ADDR(PAGE_TMDSB, 0xEA), MAN_RGB_SET = PAGE_ADDR(PAGE_TMDSB, 0xEB),
  TIMER_ENCODED = PAGE_ADDR(PAGE_TMDSB, 0xEC), RATE_REFTIM_MSB = PAGE_ADDR(PAGE_TMDSB, 0xED), RATE_REFTIM_LSB = PAGE_ADDR(PAGE_TMDSB, 0xEE), SUS_CLOCK_GOOD = PAGE_ADDR(PAGE_TMDSB, 0xEF),
  SUS_FREQ_DIGITAL_MSB = PAGE_ADDR(PAGE_TMDSB, 0xF0), SUS_FREQ_DIGITAL_ISB = PAGE_ADDR(PAGE_TMDSB, 0xF1), SUS_FREQ_DIGITAL_LSB = PAGE_ADDR(PAGE_TMDSB, 0xF2), SUS_GAIN_LIM = PAGE_ADDR(PAGE_TMDSB, 0xF3),
  SOFT_AFC_CTRL = PAGE_ADDR(PAGE_14, 0x00), SOFT_AFC_LSB = PAGE_ADDR(PAGE_14, 0x01), FIFO_LATENCY_CTRL = PAGE_ADDR(PAGE_14, 0x02), FIFO_LATENCY_VALUE = PAGE_ADDR(PAGE_14, 0x03),
  FIFO_CTRL_COEFF0 = PAGE_ADDR(PAGE_14, 0x04), FIFO_CTRL_COEFF1 = PAGE_ADDR(PAGE_14, 0x05), FIFO_CTRL_COEFF2 = PAGE_ADDR(PAGE_14, 0x06), AFC_ODPRX_MSB = PAGE_ADDR(PAGE_14, 0x07),
  AFC_ODPRX_LSB = PAGE_ADDR(PAGE_14, 0x08), DPRX_MIN = PAGE_ADDR(PAGE_14, 0x09), DPRX_MAX = PAGE_ADDR(PAGE_14, 0x0A), DPRX_LSB_MIN_MAX = PAGE_ADDR(PAGE_14, 0x0B),
  FIFO_LATENCY_VALUE_RD = PAGE_ADDR(PAGE_14, 0x0C), FIFO_CTRL_COEFF0_RD = PAGE_ADDR(PAGE_14, 0x0D), FIFO_CTRL_COEFF1_RD = PAGE_ADDR(PAGE_14, 0x0E), FIFO_CTRL_COEFF2_RD = PAGE_ADDR(PAGE_14, 0x0F),
  AUDIO_PWR_CTRL = PAGE_ADDR(PAGE_14, 0x10), AUDIO_CLOCK_MODE = PAGE_ADDR(PAGE_14, 0x11), AUDIO_HSPLL_CTRL = PAGE_ADDR(PAGE_14, 0x12), TEST_NCTS_CTRL = PAGE_ADDR(PAGE_14, 0x15),
  TEST_CTS_CHECKED_MSB = PAGE_ADDR(PAGE_14, 0x1A), TEST_CTS_CHECKED_ISB = PAGE_ADDR(PAGE_14, 0x1B), TEST_CTS_CHECKED_LSB = PAGE_ADDR(PAGE_14, 0x1C), TEST_N_CHECKED_MSB = PAGE_ADDR(PAGE_14, 0x1D),
  TEST_N_CHECKED_ISB = PAGE_ADDR(PAGE_14, 0x1E), TEST_N_CHECKED_LSB = PAGE_ADDR(PAGE_14, 0x1F), TEST_NCTS_CHECKED_VALID = PAGE_ADDR(PAGE_14, 0x20), TEST_FDET_QUOTIENT_MSB = PAGE_ADDR(PAGE_14, 0x24),
  TEST_FDET_QUOTIENT_LSB = PAGE_ADDR(PAGE_14, 0x25), TEST_AUDIO_FREQ = PAGE_ADDR(PAGE_14, 0x26), TEST_Q_DIV_SYNC = PAGE_ADDR(PAGE_14, 0x2C), TEST_R_DIV_SYNC_MSB = PAGE_ADDR(PAGE_14, 0x2D),
  TEST_R_DIV_SYNC_NSB = PAGE_ADDR(PAGE_14, 0x2E), TEST_R_DIV_SYNC_ISB = PAGE_ADDR(PAGE_14, 0x2F), TEST_R_DIV_SYNC_LSB = PAGE_ADDR(PAGE_14, 0x30), TEST_N_DIV_SYNC_MSB = PAGE_ADDR(PAGE_14, 0x31),
  TEST_N_DIV_SYNC_NSB = PAGE_ADDR(PAGE_14, 0x32), TEST_N_DIV_SYNC_ISB = PAGE_ADDR(PAGE_14, 0x33), TEST_N_DIV_SYNC_LSB = PAGE_ADDR(PAGE_14, 0x34), TEST_MODE = PAGE_ADDR(PAGE_14, 0x37),
  NCTS_CHECKED_VALID_OUT = PAGE_ADDR(PAGE_14, 0x3D), CTS_CHECKED_MSB_OUT = PAGE_ADDR(PAGE_14, 0x3E), CTS_CHECKED_ISB_OUT = PAGE_ADDR(PAGE_14, 0x3F), CTS_CHECKED_LSB_OUT = PAGE_ADDR(PAGE_14, 0x40),
  N_CHECKED_MSB_OUT = PAGE_ADDR(PAGE_14, 0x41), N_CHECKED_ISB_OUT = PAGE_ADDR(PAGE_14, 0x42), N_CHECKED_LSB_OUT = PAGE_ADDR(PAGE_14, 0x43), FDET_QUOTIENT_MSB_OUT = PAGE_ADDR(PAGE_14, 0x47),
  FDET_QUOTIENT_LSB_OUT = PAGE_ADDR(PAGE_14, 0x48), FDET_REMAIN_MSB_OUT = PAGE_ADDR(PAGE_14, 0x4A), FDET_REMAIN_ISB_OUT = PAGE_ADDR(PAGE_14, 0x4B), FDET_REMAIN_LSB_OUT = PAGE_ADDR(PAGE_14, 0x4C),
  AUDIO_STATUS = PAGE_ADDR(PAGE_14, 0x4D), Q_DIV_SYNC_OUT = PAGE_ADDR(PAGE_14, 0x51), R_DIV_SYNC_MSB = PAGE_ADDR(PAGE_14, 0x52), R_DIV_SYNC_NSB = PAGE_ADDR(PAGE_14, 0x53),
  R_DIV_SYNC_ISB = PAGE_ADDR(PAGE_14, 0x54), R_DIV_SYNC_LSB = PAGE_ADDR(PAGE_14, 0x55), N_DIV_SYNC_MSB = PAGE_ADDR(PAGE_14, 0x56), N_DIV_SYNC_NSB = PAGE_ADDR(PAGE_14, 0x57),
  N_DIV_SYNC_ISB = PAGE_ADDR(PAGE_14, 0x58), N_DIV_SYNC_LSB = PAGE_ADDR(PAGE_14, 0x59), AUDIO_PLL_STATUS = PAGE_ADDR(PAGE_14, 0x5A), CTS_MSB = PAGE_ADDR(PAGE_14, 0x5F),
  CTS_ISB = PAGE_ADDR(PAGE_14, 0x60), CTS_LSB = PAGE_ADDR(PAGE_14, 0x61), N_MSB = PAGE_ADDR(PAGE_14, 0x62), N_ISB = PAGE_ADDR(PAGE_14, 0x63),
  N_LSB = PAGE_ADDR(PAGE_14, 0x64), EDID_IN_BYTE0 = PAGE_ADDR(PAGE_EDIDA, 0x00), EDID_IN_CHECKSUM0 = PAGE_ADDR(PAGE_EDIDA, 0x7F), EDID_IN_VERSION = PAGE_ADDR(PAGE_EDIDA, 0x80),
  EDID_ENABLE = PAGE_ADDR(PAGE_EDIDA, 0x81), EDID_BLOCK_SELECT = PAGE_ADDR(PAGE_EDIDA, 0x82), HPD_POWER = PAGE_ADDR(PAGE_EDIDA, 0x84), HPD_AUTO_CTRL = PAGE_ADDR(PAGE_EDIDA, 0x85),
  HPD_DURATION = PAGE_ADDR(PAGE_EDIDA, 0x86), RX_HPD_HEAC = PAGE_ADDR(PAGE_EDIDA, 0x87), EDID_BLOCK0_TEST1 = PAGE_ADDR(PAGE_EDIDA, 0x8D), EDID_BLOCK0_TEST2 = PAGE_ADDR(PAGE_EDIDA, 0x8E),
  EDID_BLOCK0_TEST3 = PAGE_ADDR(PAGE_EDIDA, 0x8F), EDID_IN_BYTE128 = PAGE_ADDR(PAGE_EDIDB, 0x00), EDID_IN_CHECKSUM1 = PAGE_ADDR(PAGE_EDIDB, 0x7F), EDID_IN_SPA_SUB = PAGE_ADDR(PAGE_EDIDB, 0x80),
  EDID_IN_SPA_AB_A = PAGE_ADDR(PAGE_EDIDB, 0x81), EDID_IN_SPA_CD_A = PAGE_ADDR(PAGE_EDIDB, 0x82), EDID_IN_CHECKSUM_A = PAGE_ADDR(PAGE_EDIDB, 0x83), EDID_IN_SPA_AB_B = PAGE_ADDR(PAGE_EDIDB, 0x84),
  EDID_IN_SPA_CD_B = PAGE_ADDR(PAGE_EDIDB, 0x85), EDID_IN_CHECKSUM_B = PAGE_ADDR(PAGE_EDIDB, 0x86), EDID_BLOCK1_TEST1 = PAGE_ADDR(PAGE_EDIDB, 0x8D), EDID_BLOCK1_TEST2 = PAGE_ADDR(PAGE_EDIDB, 0x8E),
  EDID_BLOCK1_TEST3 = PAGE_ADDR(PAGE_EDIDB, 0x8F), RT_AUTO_CTRL = PAGE_ADDR(PAGE_CMTP, 0x00), EQ_MAN_CTRL0 = PAGE_ADDR(PAGE_CMTP, 0x01), EQ_MAN_CTRL1 = PAGE_ADDR(PAGE_CMTP, 0x02),
  OUTPUT_CFG = PAGE_ADDR(PAGE_CMTP, 0x03), MUTE_CTRL = PAGE_ADDR(PAGE_CMTP, 0x04), SLAVE_ADDR = PAGE_ADDR(PAGE_CMTP, 0x05), CMTP_REG6 = PAGE_ADDR(PAGE_CMTP, 0x06),
  CMTP_REG2F = PAGE_ADDR(PAGE_CMTP, 0x2F), CMTP_RESET = PAGE_ADDR(PAGE_CMTP, 0x33), CMTP_ADDRESS_SETUP = PAGE_ADDR(PAGE_CMTP, 0x34), CMTP_ADDRESS_HOLD = PAGE_ADDR(PAGE_CMTP, 0x35),
  CMTP_READ_ENABLE = PAGE_ADDR(PAGE_CMTP, 0x36), CMTP_WRITE_ENABLE = PAGE_ADDR(PAGE_CMTP, 0x37), CMTP_INITIALIZATION = PAGE_ADDR(PAGE_CMTP, 0x38), CMTP_ERASE_PGM_PROGRESS = PAGE_ADDR(PAGE_CMTP, 0x39),
  CMTP_DISCHARGE = PAGE_ADDR(PAGE_CMTP, 0x3A), CMTP_VANALOG = PAGE_ADDR(PAGE_CMTP, 0x3B), CMTP_TEST = PAGE_ADDR(PAGE_CMTP, 0x3C), CMTP_MEM_REGS = PAGE_ADDR(PAGE_CMTP, 0x40),
  CMTP_DMA_CONF = PAGE_ADDR(PAGE_CMTP, 0x41), CMTP_ECC_REGISTERS = PAGE_ADDR(PAGE_CMTP, 0x42), CMTP_ERR_ADDR = PAGE_ADDR(PAGE_CMTP, 0x43), CMTP_PARAM = PAGE_ADDR(PAGE_CMTP, 0x44),
  MTP_SEED_INDEX = PAGE_ADDR(PAGE_MTPA, 0x00), MTP_KEY_SPARE = PAGE_ADDR(PAGE_MTPA, 0x01), MTP_KEY39_LSB = PAGE_ADDR(PAGE_MTPA, 0x02), MTP_BKSV4 = PAGE_ADDR(PAGE_MTPA, 0x03),
  MTP_BKSV3 = PAGE_ADDR(PAGE_MTPA, 0x04), MTP_BKSV2 = PAGE_ADDR(PAGE_MTPA, 0x05), MTP_BKSV1 = PAGE_ADDR(PAGE_MTPA, 0x06), MTP_BKSV0 = PAGE_ADDR(PAGE_MTPA, 0x07),
  MTP_KEY0_MSB = PAGE_ADDR(PAGE_MTPA, 0x08), MTP_KEY0_ISB1 = PAGE_ADDR(PAGE_MTPA, 0x09), MTP_KEY0_LSB = PAGE_ADDR(PAGE_MTPA, 0x0E), MTP_KEY1_MSB = PAGE_ADDR(PAGE_MTPA, 0x0F),
  MTP_KEY1_ISB1 = PAGE_ADDR(PAGE_MTPA, 0x10), MTP_KEY1_LSB = PAGE_ADDR(PAGE_MTPA, 0x15), MTP_KEY2_MSB = PAGE_ADDR(PAGE_MTPA, 0x16), MTP_KEY2_ISB1 = PAGE_ADDR(PAGE_MTPA, 0x17),
  MTP_KEY2_LSB = PAGE_ADDR(PAGE_MTPA, 0x1C), MTP_KEY3_MSB = PAGE_ADDR(PAGE_MTPA, 0x1D), MTP_KEY3_ISB1 = PAGE_ADDR(PAGE_MTPA, 0x1E), MTP_KEY3_LSB = PAGE_ADDR(PAGE_MTPA, 0x23),
  MTP_KEY4_MSB = PAGE_ADDR(PAGE_MTPA, 0x24), MTP_KEY4_ISB1 = PAGE_ADDR(PAGE_MTPA, 0x25), MTP_KEY4_LSB = PAGE_ADDR(PAGE_MTPA, 0x2A), MTP_KEY5_MSB = PAGE_ADDR(PAGE_MTPA, 0x2B),
  MTP_KEY5_ISB1 = PAGE_ADDR(PAGE_MTPA, 0x2C), MTP_KEY5_LSB = PAGE_ADDR(PAGE_MTPA, 0x31), MTP_KEY6_MSB = PAGE_ADDR(PAGE_MTPA, 0x32), MTP_KEY6_ISB1 = PAGE_ADDR(PAGE_MTPA, 0x33),
  MTP_KEY6_LSB = PAGE_ADDR(PAGE_MTPA, 0x38), MTP_KEY7_MSB = PAGE_ADDR(PAGE_MTPA, 0x39), MTP_KEY7_ISB1 = PAGE_ADDR(PAGE_MTPA, 0x3A), MTP_KEY7_LSB = PAGE_ADDR(PAGE_MTPA, 0x3F),
  MTP_KEY8_MSB = PAGE_ADDR(PAGE_MTPA, 0x40), MTP_KEY8_ISB1 = PAGE_ADDR(PAGE_MTPA, 0x41), MTP_KEY8_LSB = PAGE_ADDR(PAGE_MTPA, 0x46), MTP_KEY9_MSB = PAGE_ADDR(PAGE_MTPA, 0x47),
  MTP_KEY9_ISB1 = PAGE_ADDR(PAGE_MTPA, 0x48), MTP_KEY9_LSB = PAGE_ADDR(PAGE_MTPA, 0x4D), MTP_KEY10_MSB = PAGE_ADDR(PAGE_MTPA, 0x4E), MTP_KEY10_ISB1 = PAGE_ADDR(PAGE_MTPA, 0x4F),
  MTP_KEY10_LSB = PAGE_ADDR(PAGE_MTPA, 0x54), MTP_KEY11_MSB = PAGE_ADDR(PAGE_MTPA, 0x55), MTP_KEY11_ISB1 = PAGE_ADDR(PAGE_MTPA, 0x56), MTP_KEY11_LSB = PAGE_ADDR(PAGE_MTPA, 0x5B),
  MTP_KEY12_MSB = PAGE_ADDR(PAGE_MTPA, 0x5C), MTP_KEY12_ISB1 = PAGE_ADDR(PAGE_MTPA, 0x5D), MTP_KEY12_LSB = PAGE_ADDR(PAGE_MTPB, 0x02), MTP_KEY13_MSB = PAGE_ADDR(PAGE_MTPB, 0x03),
  MTP_KEY13_ISB1 = PAGE_ADDR(PAGE_MTPB, 0x04), MTP_KEY13_ISB2 = PAGE_ADDR(PAGE_MTPB, 0x05), MTP_KEY13_ISB3 = PAGE_ADDR(PAGE_MTPB, 0x06), MTP_KEY13_ISB4 = PAGE_ADDR(PAGE_MTPB, 0x07),
  MTP_KEY13_ISB5 = PAGE_ADDR(PAGE_MTPB, 0x08), MTP_KEY13_LSB = PAGE_ADDR(PAGE_MTPB, 0x09), MTP_KEY14_MSB = PAGE_ADDR(PAGE_MTPB, 0x0A), MTP_KEY14_ISB1 = PAGE_ADDR(PAGE_MTPB, 0x0B),
  MTP_KEY14_ISB2 = PAGE_ADDR(PAGE_MTPB, 0x0C), MTP_KEY14_ISB3 = PAGE_ADDR(PAGE_MTPB, 0x0D), MTP_KEY14_ISB4 = PAGE_ADDR(PAGE_MTPB, 0x0E), MTP_KEY14_ISB5 = PAGE_ADDR(PAGE_MTPB, 0x0F),
  MTP_KEY14_LSB = PAGE_ADDR(PAGE_MTPB, 0x10), MTP_KEY15_MSB = PAGE_ADDR(PAGE_MTPB, 0x11), MTP_KEY15_ISB1 = PAGE_ADDR(PAGE_MTPB, 0x12), MTP_KEY15_ISB2 = PAGE_ADDR(PAGE_MTPB, 0x13),
  MTP_KEY15_ISB3 = PAGE_ADDR(PAGE_MTPB, 0x14), MTP_KEY15_ISB4 = PAGE_ADDR(PAGE_MTPB, 0x15), MTP_KEY15_ISB5 = PAGE_ADDR(PAGE_MTPB, 0x16), MTP_KEY15_LSB = PAGE_ADDR(PAGE_MTPB, 0x17),
  MTP_KEY16_MSB = PAGE_ADDR(PAGE_MTPB, 0x18), MTP_KEY16_ISB1 = PAGE_ADDR(PAGE_MTPB, 0x19), MTP_KEY16_ISB2 = PAGE_ADDR(PAGE_MTPB, 0x1A), MTP_KEY16_ISB3 = PAGE_ADDR(PAGE_MTPB, 0x1B),
  MTP_KEY16_ISB4 = PAGE_ADDR(PAGE_MTPB, 0x1C), MTP_KEY16_ISB5 = PAGE_ADDR(PAGE_MTPB, 0x1D), MTP_KEY16_LSB = PAGE_ADDR(PAGE_MTPB, 0x1E), MTP_KEY17_MSB = PAGE_ADDR(PAGE_MTPB, 0x1F),
  MTP_KEY17_ISB1 = PAGE_ADDR(PAGE_MTPB, 0x20), MTP_KEY17_ISB2 = PAGE_ADDR(PAGE_MTPB, 0x21), MTP_KEY17_ISB3 = PAGE_ADDR(PAGE_MTPB, 0x22), MTP_KEY17_ISB4 = PAGE_ADDR(PAGE_MTPB, 0x23),
  MTP_KEY17_ISB5 = PAGE_ADDR(PAGE_MTPB, 0x24), MTP_KEY17_LSB = PAGE_ADDR(PAGE_MTPB, 0x25), MTP_KEY18_MSB = PAGE_ADDR(PAGE_MTPB, 0x26), MTP_KEY18_ISB1 = PAGE_ADDR(PAGE_MTPB, 0x27),
  MTP_KEY18_ISB2 = PAGE_ADDR(PAGE_MTPB, 0x28), MTP_KEY18_ISB3 = PAGE_ADDR(PAGE_MTPB, 0x29), MTP_KEY18_ISB4 = PAGE_ADDR(PAGE_MTPB, 0x2A), MTP_KEY18_ISB5 = PAGE_ADDR(PAGE_MTPB, 0x2B),
  MTP_KEY18_LSB = PAGE_ADDR(PAGE_MTPB, 0x2C), MTP_KEY19_MSB = PAGE_ADDR(PAGE_MTPB, 0x2D), MTP_KEY19_ISB1 = PAGE_ADDR(PAGE_MTPB, 0x2E), MTP_KEY19_LSB = PAGE_ADDR(PAGE_MTPB, 0x33),
  MTP_KEY20_MSB = PAGE_ADDR(PAGE_MTPB, 0x34), MTP_KEY20_ISB1 = PAGE_ADDR(PAGE_MTPB, 0x35), MTP_KEY20_LSB = PAGE_ADDR(PAGE_MTPB, 0x3A), MTP_KEY21_MSB = PAGE_ADDR(PAGE_MTPB, 0x3B),
  MTP_KEY21_ISB1 = PAGE_ADDR(PAGE_MTPB, 0x3C), MTP_KEY21_LSB = PAGE_ADDR(PAGE_MTPB, 0x41), MTP_KEY22_MSB = PAGE_ADDR(PAGE_MTPB, 0x42), MTP_KEY22_ISB1 = PAGE_ADDR(PAGE_MTPB, 0x43),
  MTP_KEY22_LSB = PAGE_ADDR(PAGE_MTPB, 0x48), MTP_KEY23_MSB = PAGE_ADDR(PAGE_MTPB, 0x49), MTP_KEY23_ISB1 = PAGE_ADDR(PAGE_MTPB, 0x4A), MTP_KEY23_LSB = PAGE_ADDR(PAGE_MTPB, 0x4F),
  MTP_KEY24_MSB = PAGE_ADDR(PAGE_MTPB, 0x50), MTP_KEY24_ISB1 = PAGE_ADDR(PAGE_MTPB, 0x51), MTP_KEY24_LSB = PAGE_ADDR(PAGE_MTPB, 0x56), MTP_KEY25_MSB = PAGE_ADDR(PAGE_MTPB, 0x57),
  MTP_KEY25_ISB1 = PAGE_ADDR(PAGE_MTPB, 0x58), MTP_KEY25_LSB = PAGE_ADDR(PAGE_MTPB, 0x5D), MTP_KEY26_MSB = PAGE_ADDR(PAGE_MTPB, 0x5E), MTP_KEY26_ISB1 = PAGE_ADDR(PAGE_MTPB, 0x5F),
  MTP_KEY26_LSB = PAGE_ADDR(PAGE_MTPC, 0x04), MTP_KEY27_MSB = PAGE_ADDR(PAGE_MTPC, 0x05), MTP_KEY27_ISB1 = PAGE_ADDR(PAGE_MTPC, 0x06), MTP_KEY27_ISB2 = PAGE_ADDR(PAGE_MTPC, 0x07),
  MTP_KEY27_ISB3 = PAGE_ADDR(PAGE_MTPC, 0x08), MTP_KEY27_ISB4 = PAGE_ADDR(PAGE_MTPC, 0x09), MTP_KEY27_ISB5 = PAGE_ADDR(PAGE_MTPC, 0x0A), MTP_KEY27_LSB = PAGE_ADDR(PAGE_MTPC, 0x0B),
  MTP_KEY28_MSB = PAGE_ADDR(PAGE_MTPC, 0x0C), MTP_KEY28_ISB1 = PAGE_ADDR(PAGE_MTPC, 0x0D), MTP_KEY28_ISB2 = PAGE_ADDR(PAGE_MTPC, 0x0E), MTP_KEY28_ISB3 = PAGE_ADDR(PAGE_MTPC, 0x0F),
  MTP_KEY28_ISB4 = PAGE_ADDR(PAGE_MTPC, 0x10), MTP_KEY28_ISB5 = PAGE_ADDR(PAGE_MTPC, 0x11), MTP_KEY28_LSB = PAGE_ADDR(PAGE_MTPC, 0x12), MTP_KEY29_MSB = PAGE_ADDR(PAGE_MTPC, 0x13),
  MTP_KEY29_ISB1 = PAGE_ADDR(PAGE_MTPC, 0x14), MTP_KEY29_ISB2 = PAGE_ADDR(PAGE_MTPC, 0x15), MTP_KEY29_ISB3 = PAGE_ADDR(PAGE_MTPC, 0x16), MTP_KEY29_ISB4 = PAGE_ADDR(PAGE_MTPC, 0x17),
  MTP_KEY29_ISB5 = PAGE_ADDR(PAGE_MTPC, 0x18), MTP_KEY29_LSB = PAGE_ADDR(PAGE_MTPC, 0x19), MTP_KEY30_MSB = PAGE_ADDR(PAGE_MTPC, 0x1A), MTP_KEY30_ISB1 = PAGE_ADDR(PAGE_MTPC, 0x1B),
  MTP_KEY30_LSB = PAGE_ADDR(PAGE_MTPC, 0x20), MTP_KEY31_MSB = PAGE_ADDR(PAGE_MTPC, 0x21), MTP_KEY31_ISB1 = PAGE_ADDR(PAGE_MTPC, 0x22), MTP_KEY31_LSB = PAGE_ADDR(PAGE_MTPC, 0x27),
  MTP_KEY32_MSB = PAGE_ADDR(PAGE_MTPC, 0x28), MTP_KEY32_ISB1 = PAGE_ADDR(PAGE_MTPC, 0x29), MTP_KEY32_LSB = PAGE_ADDR(PAGE_MTPC, 0x2E), MTP_KEY33_MSB = PAGE_ADDR(PAGE_MTPC, 0x2F),
  MTP_KEY33_ISB1 = PAGE_ADDR(PAGE_MTPC, 0x30), MTP_KEY33_LSB = PAGE_ADDR(PAGE_MTPC, 0x35), MTP_KEY34_MSB = PAGE_ADDR(PAGE_MTPC, 0x36), MTP_KEY34_ISB1 = PAGE_ADDR(PAGE_MTPC, 0x37),
  MTP_KEY34_LSB = PAGE_ADDR(PAGE_MTPC, 0x3C), MTP_KEY35_MSB = PAGE_ADDR(PAGE_MTPC, 0x3D), MTP_KEY35_ISB1 = PAGE_ADDR(PAGE_MTPC, 0x3E), MTP_KEY35_LSB = PAGE_ADDR(PAGE_MTPC, 0x43),
  MTP_KEY36_MSB = PAGE_ADDR(PAGE_MTPC, 0x44), MTP_KEY36_ISB1 = PAGE_ADDR(PAGE_MTPC, 0x45), MTP_KEY36_LSB = PAGE_ADDR(PAGE_MTPC, 0x4A), MTP_KEY37_MSB = PAGE_ADDR(PAGE_MTPC, 0x4B),
  MTP_KEY37_ISB1 = PAGE_ADDR(PAGE_MTPC, 0x4C), MTP_KEY37_LSB = PAGE_ADDR(PAGE_MTPC, 0x51), MTP_KEY38_MSB = PAGE_ADDR(PAGE_MTPC, 0x52), MTP_KEY38_ISB1 = PAGE_ADDR(PAGE_MTPC, 0x53),
  MTP_KEY38_LSB = PAGE_ADDR(PAGE_MTPC, 0x58), MTP_KEY39_MSB = PAGE_ADDR(PAGE_MTPC, 0x59), MTP_KEY39_ISB1 = PAGE_ADDR(PAGE_MTPC, 0x5A), MTP_PRIVATE_AREA = PAGE_ADDR(PAGE_MTPC, 0x5F),
  CURPAGE = PAGE_ADDR(PAGE_INVALID, 0xFF)
}
 
enum  cec_reg {
  APRCSR = 0x00, CER = 0x01, CVR = 0x02, CCR = 0x03,
  ACKH = 0x04, ACKL = 0x05, CCONR = 0x06, CDR0 = 0x07,
  CDR1 = 0x08, CDR2 = 0x09, CDR3 = 0x0A, CDR4 = 0x0B,
  CDR5 = 0x0C, CDR6 = 0x0D, CDR7 = 0x0E, CDR8 = 0x0F,
  CDR9 = 0x10, CDR10 = 0x11, CDR11 = 0x12, CDR12 = 0x13,
  CDR13 = 0x14, CDR14 = 0x15, CDR15 = 0x16, CDR16 = 0x17,
  CDR17 = 0x18, CDR18 = 0x19, I2C_HIGH_SPEED = 0xF0, XTAL_CTRL = 0xF1,
  RESET_CTRL = 0xF2, CFG_CLK_CTRL = 0xF3, PWR_CONTROL = 0xF4, OSC_DIVIDER = 0xF5,
  OSC_PERIOD_LSB = 0xF6, OSC_PERIOD_MSB = 0xF7, EN_OSC_PERIOD_LSB = 0xF8, EN_OSC_PERIOD_MSB = 0xF9,
  STATUS_RX_SENSE = 0xFA, INTERRUPT = 0xFC, ENABLE_INTERRUPT = 0xFD, EN_RX_SENSE = 0xFE,
  CONTROL = 0xFF
}
 
enum  info_type {
  INFOFRAME_TYPE_NONE = 0x00, INFOFRAME_TYPE_VENDOR = 0x81, INFOFRAME_TYPE_AVI = 0x82, INFOFRAME_TYPE_SPD = 0x83,
  INFOFRAME_TYPE_AUDIO = 0x84, INFOFRAME_TYPE_MPS = 0x85
}
 
enum  info_spd_src {
  INFOFRAME_SPD_UNKNOWN = 0x00, INFOFRAME_SPD_DIGSTB = 0x01, INFOFRAME_SPD_DVD = 0x02, INFOFRAME_SPD_DVHS = 0x03,
  INFOFRAME_SPD_HDDVR = 0x04, INFOFRAME_SPD_DVC = 0x05, INFOFRAME_SPD_DSC = 0x06, INFOFRAME_SPD_VIDEOCD = 0x07,
  INFOFRAME_SPD_GAME = 0x08, INFOFRAME_SPD_PC = 0x09, INFOFRAME_SPD_BLURAY = 0x0A, INFOFRAME_SPD_SACD = 0x0B,
  INFOFRAME_SPD_HDDVD = 0x0C, INFOFRAME_SPD_PMP = 0x0D
}
 
enum  tda1997x_filters_ctrl_prefil { FILTERS_CTRL_PREFILTER_OFF = 0x00, FILTERS_CTRL_PREFILTER_2TAPS = 0x01, FILTERS_CTRL_PREFILTER_7TAPS = 0X02, FILTERS_CTRL_PREFILTER_27TAPS = 0x03 }
 
enum  tda1997x_of_ctrl_format { OF_CTRL_FORMAT_444 = 0x00, OF_CTRL_FORMAT_422_SMP = 0x01, OF_CTRL_FORMAT_422_CCIR = 0x02 }
 
enum  tda1997x_vid_fmt { VIDEO_FORMAT_444, VIDEO_FORMAT_422_SMP, VIDEO_FORMAT_422_CCIR }
 TDA1997X video format. More...
 

Functions

static int tda1997x_write (struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t len, uint8_t *data)
 Write Data. More...
 
static int tda1997x_read (struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t len, uint8_t *data)
 Read Data. More...
 
static int read_reg (struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t *data)
 Read Register. More...
 
static int write_reg (struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t data)
 Write Register. More...
 
static int write_reg_mask (struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t mask, uint8_t val)
 Register Mask Write Write a specified value with specified mask bits to a register. More...
 
static int tda1997x_cec_write (struct tda1997x_dev *dev, enum cec_reg reg, uint8_t len, uint8_t *data)
 CEC Write Data. More...
 
static int tda1997x_cec_read (struct tda1997x_dev *dev, enum cec_reg reg, uint8_t len, uint8_t *data)
 CEC Read Data. More...
 
static int cec_write_reg (struct tda1997x_dev *dev, enum cec_reg reg, uint8_t data)
 CEC Write Register. More...
 
static int cec_read_reg (struct tda1997x_dev *dev, enum cec_reg reg, uint8_t *data)
 CEC Read Register. More...
 
static int cec_write_reg_mask (struct tda1997x_dev *dev, enum cec_reg reg, uint8_t mask, uint8_t val)
 CEC Register Mask Write Write a specified value with specified mask bits to a register. More...
 
static int tda1997x_clear_irq (struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t *val)
 Clear Interrupt Register. More...
 
static int tda1997x_soft_rst (struct tda1997x_dev *dev, uint8_t rst)
 Software Reset. More...
 
static int tda1997x_info_rst (struct tda1997x_dev *dev, uint8_t rst)
 Infoframe Reset. More...
 
static int tda1997x_sus_en (struct tda1997x_dev *dev, uint8_t en)
 Enable Startup Sequence. More...
 
int tda1997x_cfg_vp (struct tda1997x_dev *dev, uint8_t *vp_conf)
 Configure Video Port. More...
 
int tda1997x_cfg_conv (struct tda1997x_dev *dev, int16_t *mtx)
 Configure Colorspace Conversion. More...
 
int tda1997x_cfg_vid_out (struct tda1997x_dev *dev)
 Configure Video Output Format. More...
 
int tda1997x_cfg_prefilter (struct tda1997x_dev *dev, enum tda1997x_filters_ctrl_prefil bu, enum tda1997x_filters_ctrl_prefil rv)
 Configure Prefilter. More...
 
int tda1997x_cfg_audio_fmt (struct tda1997x_dev *dev)
 Configure Audio Format. More...
 
int tda1997x_cfg_audio_mode (struct tda1997x_dev *dev, enum tda1997x_audio_sel_mode mode)
 Configure Audio Selection. More...
 
int tda1997x_get_audio_flags (struct tda1997x_dev *dev, uint8_t *status)
 Get Audio Status. More...
 
int tda1997x_get_audio_freq (struct tda1997x_dev *dev, enum tda1997x_audio_freq *freq)
 Get Audio Frequency. More...
 
int tda1997x_get_chan_status (struct tda1997x_dev *dev)
 Get Audio Channel Status. More...
 
static int tda1997x_audio_fifo_rst (struct tda1997x_dev *dev)
 Reset Audio FIFO. More...
 
static int tda1997x_edid_cksum (struct tda1997x_dev *dev, uint8_t *edid, uint8_t *cksum)
 Calculate EDID Block Checksum. More...
 
int tda1997x_cfg_edid (struct tda1997x_dev *dev, uint8_t *edid, uint8_t *edid_ext)
 Configure EDID. More...
 
static int tda1997x_cfg_spa (struct tda1997x_dev *dev, uint8_t *edid1, uint8_t offset, uint16_t *spa)
 Configure Source Physical Address. More...
 
static int tda1997x_read_infoframe (struct tda1997x_dev *dev, enum hdmi_reg reg, union tda1997x_infoframe *info)
 Read Infoframe. More...
 
int tda1997x_parse_infoframe (struct tda1997x_dev *dev, union tda1997x_infoframe *info)
 Parse Infoframe. More...
 
int tda1997x_parse_aud_infoframe (struct tda1997x_dev *dev, struct tda1997x_info_aud *info)
 Parse Audio Infoframe. More...
 
int tda1997x_print_infoframe (struct tda1997x_dev *dev)
 Print Infoframe. More...
 
int tda1997x_get_timing (struct tda1997x_dev *dev, uint8_t *data)
 Get Timing Values Sets an data memory block to the video timing register values. More...
 
int tda1997x_init (struct tda1997x_dev *dev, struct tda1997x_cfg *cfg, uint8_t *edid_block, uint8_t *edid_ext)
 Initialize TDA1997x HDMI Receiver. More...
 
static int tda1997x_sus_irq (struct tda1997x_dev *dev, uint8_t flags)
 Startup Sequence Interrupt Handler. More...
 
static int tda1997x_infoframe_irq (struct tda1997x_dev *dev, uint8_t flags)
 Parse Infoframe. More...
 
int tda1997x_audio_irq (struct tda1997x_dev *dev, uint8_t flags)
 Audio Interrupt Handler. More...
 
int tda1997x_afe_irq (struct tda1997x_dev *dev, uint8_t flags)
 AFE Interrupt Handler. More...
 
int tda1997x_handle_irq (struct tda1997x_dev *dev)
 Handle TDA1997x Interrupt. More...
 
int tda1997x_interrupt (struct tda1997x_dev *dev, struct tda1997x_irq_source *tab)
 

Variables

static uint8_t vp_conf444 [9]
 
static uint8_t vp_conf_mute [9]
 
static const uint8_t blank_rgb [6]
 
static const uint8_t blank_yuv [6]
 
static const int16_t color_conv444 [COLOR_CONV_MATRIX_LENGTH]
 
static const int16_t yuv709_rgb_full [COLOR_CONV_MATRIX_LENGTH]
 
static const int16_t yuv601_rgb_full [COLOR_CONV_MATRIX_LENGTH]
 
static const int16_t rgb_lim_rgb_full [COLOR_CONV_MATRIX_LENGTH]
 
static const int16_t rgb_lim_itu601 [COLOR_CONV_MATRIX_LENGTH]
 
static const int16_t rgb_lim_itu709 [COLOR_CONV_MATRIX_LENGTH]
 
static const int16_t rgb_full_itu601 [COLOR_CONV_MATRIX_LENGTH]
 
static const int16_t rgb_full_itu709 [COLOR_CONV_MATRIX_LENGTH]
 
static const uint8_t clk_rate [6]
 
const struct tda1997x_mtp_seed hdcp_seed_tab [TDA1997X_SEED_TABLE_LEN]
 
static uint8_t ddc_config [8]
 
static uint8_t rt_config [6]
 
static uint16_t spa_edid [2]
 

Detailed Description

Macro Definition Documentation

◆ AUDIO_CLOCK_POWER_OFF

#define AUDIO_CLOCK_POWER_OFF   (1 << 7)

#include <projects/lib/tda1997x.c>

Power down audio clocks

◆ AUDIO_CLOCK_REF_TMDS

#define AUDIO_CLOCK_REF_TMDS   (1 << 6)

#include <projects/lib/tda1997x.c>

Use TMDS as reference rather than xtal

◆ AUDIO_LAYOUT_MANUAL

#define AUDIO_LAYOUT_MANUAL   (1 << 1)

#include <projects/lib/tda1997x.c>

Manual control of layout

◆ AUDIO_LAYOUT_SP_FLAG

#define AUDIO_LAYOUT_SP_FLAG   (1 << 2)

#include <projects/lib/tda1997x.c>

SP flag used by FIFO control

◆ AUDIO_OUT_ENABLE_ACLK

#define AUDIO_OUT_ENABLE_ACLK   (1 << 5)

#include <projects/lib/tda1997x.c>

Audio clock port

◆ AUDIO_OUT_ENABLE_AP0

#define AUDIO_OUT_ENABLE_AP0   (1 << 0)

#include <projects/lib/tda1997x.c>

AP0

◆ AUDIO_OUT_ENABLE_AP1

#define AUDIO_OUT_ENABLE_AP1   (1 << 1)

#include <projects/lib/tda1997x.c>

AP1

◆ AUDIO_OUT_ENABLE_AP2

#define AUDIO_OUT_ENABLE_AP2   (1 << 2)

#include <projects/lib/tda1997x.c>

AP2

◆ AUDIO_OUT_ENABLE_AP3

#define AUDIO_OUT_ENABLE_AP3   (1 << 3)

#include <projects/lib/tda1997x.c>

AP3

◆ AUDIO_OUT_ENABLE_WS

#define AUDIO_OUT_ENABLE_WS   (1 << 4)

#include <projects/lib/tda1997x.c>

Word select port

◆ AUDIO_SEL_ACLKINV

#define AUDIO_SEL_ACLKINV   (1 << 7)

#include <projects/lib/tda1997x.c>

Invert A_CLK pin polarity

◆ AUDIO_SEL_AUTOMUTE

#define AUDIO_SEL_AUTOMUTE   (1 << 3)

#include <projects/lib/tda1997x.c>

Auto mute audio

◆ AUDIO_SEL_HBR_DEMUX

#define AUDIO_SEL_HBR_DEMUX   (1 << 2)

#include <projects/lib/tda1997x.c>

High bit rate demux

◆ AUDIO_SEL_I2S32

#define AUDIO_SEL_I2S32   (1 << 4)

#include <projects/lib/tda1997x.c>

32-bit I2S mode

◆ AUDIO_SEL_MODE_MASK

#define AUDIO_SEL_MODE_MASK   (0x03U)

#include <projects/lib/tda1997x.c>

Audio type

◆ AUDIO_SEL_SPDIF

#define AUDIO_SEL_SPDIF   (1 << 5)

#include <projects/lib/tda1997x.c>

SPDIF format

◆ AUDIO_SEL_TESTTONE

#define AUDIO_SEL_TESTTONE   (1 << 6)

#include <projects/lib/tda1997x.c>

Test tone generator

◆ CLKOUT_CLK_DELAY_MASK

#define CLKOUT_CLK_DELAY_MASK   (0x70U)

#include <projects/lib/tda1997x.c>

Clock delay on V_CLK

◆ CLKOUT_CTRL_TOGGLE_ON

#define CLKOUT_CTRL_TOGGLE_ON   (1 << 2)

#include <projects/lib/tda1997x.c>

V_CLK invert polarity

◆ DE_FREF_SEL_DELAY_MASK

#define DE_FREF_SEL_DELAY_MASK   (0xF0U)

#include <projects/lib/tda1997x.c>

Delay from HDMI to DE

◆ DE_FREF_SEL_OUT_MASK

#define DE_FREF_SEL_OUT_MASK   (0x03U)

#include <projects/lib/tda1997x.c>

Signal output selection

◆ DE_FREF_SEL_PIX_QUAL

#define DE_FREF_SEL_PIX_QUAL   (1 << 3)

#include <projects/lib/tda1997x.c>

Pixel qualification

◆ DE_FREF_SEL_POL_INV

#define DE_FREF_SEL_POL_INV   (1 << 2)

#include <projects/lib/tda1997x.c>

Invert DE signal polarity

◆ HDMI_FLAGS_AUD_FIFO_LOW

#define HDMI_FLAGS_AUD_FIFO_LOW   (1 << 0)

#include <projects/lib/tda1997x.c>

FIFO read ptr within 2 of write

◆ HDMI_FLAGS_AUD_FIFO_OVR

#define HDMI_FLAGS_AUD_FIFO_OVR   (1 << 1)

#include <projects/lib/tda1997x.c>

FIFO overflow

◆ HDMI_FLAGS_AUD_LAYOUT

#define HDMI_FLAGS_AUD_LAYOUT   (1 << 2)

#include <projects/lib/tda1997x.c>

Layout status Audio sample packet

◆ HDMI_FLAGS_AUDIO

#define HDMI_FLAGS_AUDIO   (1 << 7)

#include <projects/lib/tda1997x.c>

Audio packet in last videoframe

◆ HDMI_FLAGS_AVMUTE

#define HDMI_FLAGS_AVMUTE   (1 << 3)

#include <projects/lib/tda1997x.c>

AVMUTE

◆ HDMI_FLAGS_EESS

#define HDMI_FLAGS_EESS   (1 << 5)

#include <projects/lib/tda1997x.c>

EESS detected

◆ HDMI_FLAGS_HDCP

#define HDMI_FLAGS_HDCP   (1 << 4)

#include <projects/lib/tda1997x.c>

HDCP detected

◆ HDMI_FLAGS_HDMI

#define HDMI_FLAGS_HDMI   (1 << 6)

#include <projects/lib/tda1997x.c>

HDMI detected

◆ HDMI_SOFT_RESET_DC

#define HDMI_SOFT_RESET_DC   (1 << 7)

#include <projects/lib/tda1997x.c>

Soft reset bit

◆ HS_HREF_SEL_DELAY_MASK

#define HS_HREF_SEL_DELAY_MASK   (0xF0U)

#include <projects/lib/tda1997x.c>

Delay from HDMI to HS

◆ HS_HREF_SEL_OUT_MASK

#define HS_HREF_SEL_OUT_MASK   (0x03U)

#include <projects/lib/tda1997x.c>

Signal output selection

◆ HS_HREF_SEL_PIX_QUAL

#define HS_HREF_SEL_PIX_QUAL   (1 << 3)

#include <projects/lib/tda1997x.c>

Pixel qualification

◆ HS_HREF_SEL_POL_INV

#define HS_HREF_SEL_POL_INV   (1 << 2)

#include <projects/lib/tda1997x.c>

Invert HS signal polarity

◆ INFO_AUD_CH_COUNT_MASK

#define INFO_AUD_CH_COUNT_MASK   (0x07U)

#include <projects/lib/tda1997x.c>

Channel count

◆ INFO_AUD_CODE_TYPE_MASK

#define INFO_AUD_CODE_TYPE_MASK   (0xF0U)

#include <projects/lib/tda1997x.c>

Code type

◆ INFO_AUD_DM_INHIBIT

#define INFO_AUD_DM_INHIBIT   (1 << 7)

#include <projects/lib/tda1997x.c>

Down-mix inhibit

◆ INFO_AUD_LFE_PB_MASK

#define INFO_AUD_LFE_PB_MASK   (0x03U)

#include <projects/lib/tda1997x.c>

LFE playback level

◆ INFO_AUD_LVL_SHIFT_MASK

#define INFO_AUD_LVL_SHIFT_MASK   (0x78U)

#include <projects/lib/tda1997x.c>

Level shift value

◆ INFO_AUD_SAMPLE_FREQ_MASK

#define INFO_AUD_SAMPLE_FREQ_MASK   (0x1CU)

#include <projects/lib/tda1997x.c>

Sample frequency

◆ INFO_AUD_SAMPLE_SIZE_MASK

#define INFO_AUD_SAMPLE_SIZE_MASK   (0x03U)

#include <projects/lib/tda1997x.c>

Sample size

◆ INFO_RST_AI

#define INFO_RST_AI   (1 << 2)

#include <projects/lib/tda1997x.c>

Reset advanced infoframe

◆ INFO_RST_AUDIO

#define INFO_RST_AUDIO   (1 << 0)

#include <projects/lib/tda1997x.c>

Reset audio

◆ INFO_RST_AUDIO_FIFO

#define INFO_RST_AUDIO_FIFO   (1 << 4)

#include <projects/lib/tda1997x.c>

Reset audio FIFO

◆ INFO_RST_AUDIO_FIFO_CTRL

#define INFO_RST_AUDIO_FIFO_CTRL   (1 << 5)

#include <projects/lib/tda1997x.c>

Reset audio FIFO control

◆ INFO_RST_GAMUT

#define INFO_RST_GAMUT   (1 << 3)

#include <projects/lib/tda1997x.c>

Reset gamut

◆ INFO_RST_INFOFRAME

#define INFO_RST_INFOFRAME   (1 << 1)

#include <projects/lib/tda1997x.c>

Reset infoframe

◆ INFO_RST_NACK_HDCP

#define INFO_RST_NACK_HDCP   (1 << 7)

#include <projects/lib/tda1997x.c>

Nack HDCP

◆ IRQ_AFE_ACTIVITY_DET

#define IRQ_AFE_ACTIVITY_DET   (1 << 4)

#include <projects/lib/tda1997x.c>

Activity detected on data

◆ IRQ_AFE_ASU_READY

#define IRQ_AFE_ASU_READY   (1 << 0)

#include <projects/lib/tda1997x.c>

AFE calibration done: TMDS ready

◆ IRQ_AFE_ASU_STATE

#define IRQ_AFE_ASU_STATE   (1 << 1)

#include <projects/lib/tda1997x.c>

ASU state is reached

◆ IRQ_AFE_GAIN_DONE

#define IRQ_AFE_GAIN_DONE   (1 << 6)

#include <projects/lib/tda1997x.c>

Gain calibration done

◆ IRQ_AFE_OFFSET_DONE

#define IRQ_AFE_OFFSET_DONE   (1 << 5)

#include <projects/lib/tda1997x.c>

Offset calibration done

◆ IRQ_AFE_PLL_LOCK

#define IRQ_AFE_PLL_LOCK   (1 << 3)

#include <projects/lib/tda1997x.c>

TMDS PLL is locked

◆ IRQ_AFE_TRMCAL_DONE

#define IRQ_AFE_TRMCAL_DONE   (1 << 2)

#include <projects/lib/tda1997x.c>

Termination calibration done

◆ IRQ_AFE_WDL_UNLOCKED

#define IRQ_AFE_WDL_UNLOCKED   (1 << 7)

#include <projects/lib/tda1997x.c>

Wordlocker was unlocked

◆ OF_CTRL_OUTPUT_ACTIVE

#define OF_CTRL_OUTPUT_ACTIVE   (1 << 7)

#include <projects/lib/tda1997x.c>

Output active

◆ OF_CTRL_VIDEO_HIZ

#define OF_CTRL_VIDEO_HIZ   (1 << 6)

#include <projects/lib/tda1997x.c>

Set video port to high impedance

◆ VS_VREF_SEL_DELAY_MASK

#define VS_VREF_SEL_DELAY_MASK   (0xF0U)

#include <projects/lib/tda1997x.c>

Delay from HDMI to VS

◆ VS_VREF_SEL_OUT_MASK

#define VS_VREF_SEL_OUT_MASK   (0x03U)

#include <projects/lib/tda1997x.c>

Signal output selection

◆ VS_VREF_SEL_PIX_QUAL

#define VS_VREF_SEL_PIX_QUAL   (1 << 3)

#include <projects/lib/tda1997x.c>

Pixel qualification

◆ VS_VREF_SEL_POL_INV

#define VS_VREF_SEL_POL_INV   (1 << 2)

#include <projects/lib/tda1997x.c>

Invert VS signal polarity

Enumeration Type Documentation

◆ tda1997x_vid_fmt

enum tda1997x_vid_fmt

#include <projects/lib/tda1997x.h>

TDA1997X video format.

Enumerator
VIDEO_FORMAT_444 

Output format is full 4:4:4

VIDEO_FORMAT_422_SMP 

Output format is 4:2:2 Semi Planar

VIDEO_FORMAT_422_CCIR 

Output format is 4:2:2 CCIR 656

120  {
121  VIDEO_FORMAT_444,
122  VIDEO_FORMAT_422_SMP,
123  VIDEO_FORMAT_422_CCIR
VIDEO_FORMAT_422_CCIR
Definition: tda1997x.h:122
VIDEO_FORMAT_444
Definition: tda1997x.h:120
VIDEO_FORMAT_422_SMP
Definition: tda1997x.h:121

Function Documentation

◆ cec_read_reg()

static int cec_read_reg ( struct tda1997x_dev *  dev,
enum cec_reg  reg,
uint8_t *  data 
)
static

#include <projects/lib/tda1997x.c>

CEC Read Register.

Parameters
devTDA1997X device structure pointer
regRegister and page address
dataPointer to data to read to
Returns
0 on success, non-zero error status otherwise
1951 {
1952  return tda1997x_cec_read(dev, reg, 1, data);;
1953 }
tda1997x_cec_read
static int tda1997x_cec_read(struct tda1997x_dev *dev, enum cec_reg reg, uint8_t len, uint8_t *data)
CEC Read Data.
Definition: tda1997x.c:1913

◆ cec_write_reg()

static int cec_write_reg ( struct tda1997x_dev *  dev,
enum cec_reg  reg,
uint8_t  data 
)
static

#include <projects/lib/tda1997x.c>

CEC Write Register.

Parameters
devTDA1997X device structure pointer
regRegister and page address
dataData value to write to register
Returns
0 on success, non-zero error status otherwise
1936 {
1937  uint8_t tmp = data;
1938 
1939  return tda1997x_cec_write(dev, reg, 1, &tmp);
1940 }
tda1997x_cec_write
static int tda1997x_cec_write(struct tda1997x_dev *dev, enum cec_reg reg, uint8_t len, uint8_t *data)
CEC Write Data.
Definition: tda1997x.c:1890

◆ cec_write_reg_mask()

static int cec_write_reg_mask ( struct tda1997x_dev *  dev,
enum cec_reg  reg,
uint8_t  mask,
uint8_t  val 
)
static

#include <projects/lib/tda1997x.c>

CEC Register Mask Write Write a specified value with specified mask bits to a register.

Parameters
devTDA1997X device structure pointer
regRegister and page address
maskMask of bits to be transformed
valBitfield to be written within mask
Returns
0 on success, non-zero error status otherwise
1966 {
1967  int err;
1968  uint8_t reg_val;
1969 
1970  err = cec_read_reg(dev, reg, &reg_val);
1971  if (err < 0)
1972  return err;
1973 
1974  reg_val &= ~(mask);
1975  reg_val |= val & mask;
1976 
1977  return cec_write_reg(dev, reg, reg_val);
1978 }
cec_write_reg
static int cec_write_reg(struct tda1997x_dev *dev, enum cec_reg reg, uint8_t data)
CEC Write Register.
Definition: tda1997x.c:1935
cec_read_reg
static int cec_read_reg(struct tda1997x_dev *dev, enum cec_reg reg, uint8_t *data)
CEC Read Register.
Definition: tda1997x.c:1950

◆ read_reg()

static int read_reg ( struct tda1997x_dev *  dev,
enum hdmi_reg  reg,
uint8_t *  data 
)
static

#include <projects/lib/tda1997x.c>

Read Register.

Parameters
devTDA1997X device structure pointer
regRegister and page address
dataPointer to data to read to
Returns
Number of bytes read or less-than-zero error status
1837 {
1838  return tda1997x_read(dev, reg, 1, data);;
1839 }
tda1997x_read
static int tda1997x_read(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t len, uint8_t *data)
Read Data.
Definition: tda1997x.c:1804

◆ tda1997x_afe_irq()

int tda1997x_afe_irq ( struct tda1997x_dev *  dev,
uint8_t  flags 
)

#include <projects/lib/tda1997x.c>

AFE Interrupt Handler.

Parameters
devTDA1997X device structure pointer
flagsFlags read from the interrupt flags register
Returns
0 on success, non-zero error otherwise
3335 {
3336  return 0;
3337 }

◆ tda1997x_audio_fifo_rst()

static int tda1997x_audio_fifo_rst ( struct tda1997x_dev *  dev)
static

#include <projects/lib/tda1997x.c>

Reset Audio FIFO.

Parameters
devTDA1997X device structure pointer
Returns
0 on success, non-zero error status otherwise
2387 {
2388  int err;
2389 
2390  err = write_reg_mask(dev, HDMI_INFO_RST, INFO_RST_AUDIO_FIFO_MASK, INFO_RST_AUDIO_FIFO_MASK);
2391  if (err < 0)
2392  return err;
2393 
2394  err = write_reg_mask(dev, HDMI_INFO_RST, INFO_RST_AUDIO_FIFO_MASK, 0);
2395  if (err < 0)
2396  return err;
2397 
2398  return 0;
2399 }
write_reg_mask
static int write_reg_mask(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t mask, uint8_t val)
Register Mask Write Write a specified value with specified mask bits to a register.
Definition: tda1997x.c:1866

◆ tda1997x_audio_irq()

int tda1997x_audio_irq ( struct tda1997x_dev *  dev,
uint8_t  flags 
)

#include <projects/lib/tda1997x.c>

Audio Interrupt Handler.

Parameters
devTDA19997X device structure pointer
flagsFlags read from the interrupt flags register
Returns
0 on success, non-zero error status otherwise
3251 {
3252  int err;
3253  uint8_t status;
3254  enum tda1997x_audio_freq freq;
3255 
3256  if (flags & IRQ_AUDIO_FIFO_ERROR) {
3257 
3258  err = read_reg(dev, SUS_STATUS, &status);
3259  if (err < 0)
3260  return err;
3261 
3262  /* Last state reached */
3263  if ((status & SUS_STATUS_STATE_MASK) == SUS_STATUS_LAST_STATE) {
3264 
3265  /* Reset the audio FIFO */
3266 // err = tda1997x_audio_fifo_rst(dev);
3267 // if (err < 0)
3268 // return err;
3269  }
3270  }
3271 
3272  if (flags & IRQ_AUDIO_FIFO_UNMUTE) {
3273  /* Audio FIFO unmuted */
3274  }
3275 
3276  if ((flags & IRQ_AUDIO_CHAN_STATUS) &&
3277  !(flags & (IRQ_AUDIO_FIFO_ERROR | IRQ_AUDIO_MUTE))) {
3278 
3279  err = read_reg(dev, AUDIO_STATUS, &status);
3280  if (err < 0)
3281  return err;
3282 
3283  /* Read channel status */
3284  err = tda1997x_get_chan_status(dev);
3285  if (err < 0)
3286  return err;
3287  }
3288 
3289  if (flags & IRQ_AUDIO_MUTE) {
3290 
3291  err = read_reg(dev, SUS_STATUS, &status);
3292  if (err < 0)
3293  return err;
3294 
3295  /* Last state reached */
3296  if ((status & SUS_STATUS_STATE_MASK) == SUS_STATUS_LAST_STATE) {
3297 
3298  /* Reset the audio FIFO */
3299 // err = tda1997x_audio_fifo_rst(dev);
3300 // if (err < 0)
3301 // return err;
3302  }
3303  }
3304 
3305  if (flags & IRQ_AUDIO_FLAGS) {
3306  /* Get the audio flags */
3307  err = tda1997x_get_audio_flags(dev, &status);
3308  if (err < 0)
3309  return err;
3310  }
3311 
3312  if (flags & IRQ_AUDIO_FREQ_CHANGE) {
3313 
3314  /* Get the audio frequency */
3315  err = tda1997x_get_audio_freq(dev, &freq);
3316  if (err < 0)
3317  return err;
3318 
3319  if (freq != AUDIO_FREQ_HEADER) {
3320  }
3321  }
3322 
3323  return 0;
3324 }
tda1997x_get_audio_freq
int tda1997x_get_audio_freq(struct tda1997x_dev *dev, enum tda1997x_audio_freq *freq)
Get Audio Frequency.
Definition: tda1997x.c:2346
read_reg
static int read_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t *data)
Read Register.
Definition: tda1997x.c:1836
tda1997x_get_chan_status
int tda1997x_get_chan_status(struct tda1997x_dev *dev)
Get Audio Channel Status.
Definition: tda1997x.c:2367
tda1997x_get_audio_flags
int tda1997x_get_audio_flags(struct tda1997x_dev *dev, uint8_t *status)
Get Audio Status.
Definition: tda1997x.c:2333

◆ tda1997x_cec_read()

static int tda1997x_cec_read ( struct tda1997x_dev *  dev,
enum cec_reg  reg,
uint8_t  len,
uint8_t *  data 
)
static

#include <projects/lib/tda1997x.c>

CEC Read Data.

Parameters
devTDA1997X device structure pointer
regStart register and page address
lenLength of data to read from device
dataPointer to data to read to
Returns
0 on success, non-zero error status otherwise
1914 {
1915  int i, err;
1916  struct tda1997x_cfg *cfg = dev->cfg;
1917 
1918  for (i = 0; i < len; i++, data++) {
1919  err = cfg->i2c_read(cfg->cec_addr, (uint8_t)reg + i, data);
1920  if (err < 0)
1921  return err;
1922  }
1923 
1924  return i;
1925 }
tda1997x_cfg
TDA1997X driver configuration.
Definition: tda1997x.h:138

◆ tda1997x_cec_write()

static int tda1997x_cec_write ( struct tda1997x_dev *  dev,
enum cec_reg  reg,
uint8_t  len,
uint8_t *  data 
)
static

#include <projects/lib/tda1997x.c>

CEC Write Data.

Parameters
devTDA1997X device structure pointer
regStart register and page address
lenLength of data to write to device
dataPointer to data to write from
Returns
0 on success, non-zero error status otherwise
1891 {
1892  int i, err;
1893  struct tda1997x_cfg *cfg = dev->cfg;
1894 
1895  for (i = 0; i < len; i++, data++) {
1896  err = cfg->i2c_write(cfg->cec_addr, (uint8_t)reg + i, data);
1897  if (err < 0)
1898  return err;
1899  }
1900 
1901  return i;
1902 }
tda1997x_cfg
TDA1997X driver configuration.
Definition: tda1997x.h:138

◆ tda1997x_cfg_audio_fmt()

int tda1997x_cfg_audio_fmt ( struct tda1997x_dev *  dev)

#include <projects/lib/tda1997x.c>

Configure Audio Format.

Parameters
devTDA1997X device structure pointer
Returns
0 on success, non-zero error status otherwise

BEGIN: Configure Audio Formatter

Configure FIFO control for audio

Todo:
Determine the correct register setting for FIFO_LATENCY_CTRL that will eliminate glitches and interruptions in audio stream

END: Configure Audio Formatter

BEGIN: Configure Audio Clock Mode

END: Configure Audio Clock Mode

2224 {
2225  int err;
2226  uint8_t reg_val;
2227 
2231  /* Configure audio path */
2232  err = write_reg(dev, AUDIO_PATH, 0x01);
2233  if (err < 0)
2234  return err;
2235 
2236  /* Configure audio layout */
2237  err = write_reg(dev, AUDIO_LAYOUT, AUDIO_LAYOUT_SP_FLAG);
2238  if (err < 0)
2239  return err;
2240 
2241  /* Configure FIFO latency */
2242  err = write_reg(dev, FIFO_LATENCY_VALUE, 0x80U);
2243  if (err < 0)
2244  return err;
2245 
2251  err = write_reg(dev, FIFO_LATENCY_CTRL, 0x03);
2252  if (err < 0)
2253  return err;
2254 
2255  /* Configure audio selection */
2256  err = write_reg(dev, AUDIO_SEL, 0x00); // AUDIO_SEL_TESTTONE
2257  if (err < 0)
2258  return err;
2259 
2260  /* Configure audio enable */
2261  err = write_reg(dev,
2262  AUDIO_OUT_ENABLE,
2263  AUDIO_OUT_ENABLE_ACLK |
2264  AUDIO_OUT_ENABLE_WS |
2265  AUDIO_OUT_ENABLE_AP0);
2266 // AUDIO_OUT_ENABLE_AP1 |
2267 // AUDIO_OUT_ENABLE_AP2 |
2268 // AUDIO_OUT_ENABLE_AP3);
2269  if (err < 0)
2270  return err;
2271 
2272  err = read_reg(dev, AUDIO_OUT_LOW_HIZ, &reg_val);
2273  if (err < 0)
2274  return err;
2275 
2276  if (0) {
2277  /* Set test mode */
2278  err = write_reg(dev, TEST_MODE, 0x03);
2279  if (err < 0)
2280  return err;
2281 
2282  err = write_reg(dev, TEST_AUDIO_FREQ, 0x0b);
2283  if (err < 0)
2284  return err;
2285  } else {
2286  err = write_reg(dev, TEST_MODE, 0x00);
2287  if (err < 0)
2288  return err;
2289 
2290  err = write_reg_mask(dev, TEST_NCTS_CTRL, 0x03, 0);
2291  if (err < 0)
2292  return err;
2293  }
2302  err = write_reg(dev, AUDIO_CLOCK_MODE, (uint8_t) AUDIO_CLOCK_MODE_128FS);
2303  if (err < 0)
2304  return err;
2309  return 0;
2310 }
AUDIO_OUT_ENABLE_AP0
#define AUDIO_OUT_ENABLE_AP0
Definition: tda1997x.c:201
read_reg
static int read_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t *data)
Read Register.
Definition: tda1997x.c:1836
AUDIO_OUT_ENABLE_ACLK
#define AUDIO_OUT_ENABLE_ACLK
Definition: tda1997x.c:196
write_reg_mask
static int write_reg_mask(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t mask, uint8_t val)
Register Mask Write Write a specified value with specified mask bits to a register.
Definition: tda1997x.c:1866
AUDIO_LAYOUT_SP_FLAG
#define AUDIO_LAYOUT_SP_FLAG
Definition: tda1997x.c:192
write_reg
static int write_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t data)
Write Register.
Definition: tda1997x.c:1849
AUDIO_OUT_ENABLE_WS
#define AUDIO_OUT_ENABLE_WS
Definition: tda1997x.c:197

◆ tda1997x_cfg_audio_mode()

int tda1997x_cfg_audio_mode ( struct tda1997x_dev *  dev,
enum tda1997x_audio_sel_mode  mode 
)

#include <projects/lib/tda1997x.c>

Configure Audio Selection.

Parameters
devTDA1997X device structure pointer
modeAudio selection mode enumeration value
Returns
0 on success, non-zero error status otherwise
2321 {
2322  return write_reg_mask(dev, AUDIO_SEL, AUDIO_SEL_MODE_MASK, (uint8_t)mode);
2323 }
write_reg_mask
static int write_reg_mask(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t mask, uint8_t val)
Register Mask Write Write a specified value with specified mask bits to a register.
Definition: tda1997x.c:1866
AUDIO_SEL_MODE_MASK
#define AUDIO_SEL_MODE_MASK
Definition: tda1997x.c:190

◆ tda1997x_cfg_conv()

int tda1997x_cfg_conv ( struct tda1997x_dev *  dev,
int16_t *  mtx 
)

#include <projects/lib/tda1997x.c>

Configure Colorspace Conversion.

Parameters
devTDA1997X device structure pointer
mtxPointer to start of conversion matrix or NULL for bypass
Returns
0 on success, non-zero error status otherwise
2084 {
2085  int err;
2086  uint8_t i;
2087  uint8_t reg_val[30];
2088 
2089  /* Matrix bypass if called with NULL */
2090  if (mtx == NULL)
2091  return write_reg_mask(dev, VDP_CTRL, VDP_CTRL_MATRIX_BYPASS, VDP_CTRL_MATRIX_BYPASS);
2092 
2093  /* Turn off matrix bypass before setting the matrix coefficients */
2094  err = write_reg_mask(dev, VDP_CTRL, VDP_CTRL_MATRIX_BYPASS, 0);
2095  if (err < 0)
2096  return err;
2097 
2098  for (i = 0; i < 15; i++, mtx++) {
2099  reg_val[2 * i] = (uint8_t)((*mtx & 0xFF00) >> 8); /* coeff MSB register */
2100  reg_val[(2 * i) + 1] = (uint8_t)(((uint16_t)(*mtx)) & 0x00FF); /* coeff LSB register */
2101  }
2102 
2103  err = tda1997x_write(dev, MAT_OI1_MSB, 30, reg_val);
2104  if (err < 0)
2105  return err;
2106 
2107  return 0;
2108 }
tda1997x_write
static int tda1997x_write(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t len, uint8_t *data)
Write Data.
Definition: tda1997x.c:1767
write_reg_mask
static int write_reg_mask(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t mask, uint8_t val)
Register Mask Write Write a specified value with specified mask bits to a register.
Definition: tda1997x.c:1866

◆ tda1997x_cfg_edid()

int tda1997x_cfg_edid ( struct tda1997x_dev *  dev,
uint8_t *  edid,
uint8_t *  edid_ext 
)

#include <projects/lib/tda1997x.c>

Configure EDID.

Parameters
devTDA1997X device structure pointer
edidPointer to start of EDID block, expected to be 127 bytes
edid_extPointer to start of EDID extension, expected to be 127 bytes
Returns
0 on success, non-zero error status otherwise

< Checksum values for each EDID block and SPA

2438 {
2439  int err;
2440  uint8_t cksum;
2442  /* Check arguments */
2443  if ((dev == NULL) ||
2444  (edid == NULL) ||
2445  (edid_ext == NULL))
2446  return (-1);
2447 
2448  /* Required number of EDID extensions after EDID block */
2449  if (edid[126] != 1) {
2450  DEBUG_PRINT("invalid number of EDID extensions: %d", edid[126]);
2451  return (-3);
2452  }
2453 
2454  /* Calculate the checksum for EDID block 0 */
2455  err = tda1997x_edid_cksum(dev, edid, &cksum);
2456  if (err < 0)
2457  return err;
2458 
2459  err = tda1997x_write(dev, EDID_IN_BYTE0, 127, edid);
2460  if (err < 0)
2461  return err;
2462 
2463  /* Write block 0 checksum byte */
2464  err = write_reg(dev, EDID_IN_CHECKSUM0, cksum);
2465  if (err < 0)
2466  return err;
2467 
2468  /* Calculate the checksum for EDID extension */
2469  err = tda1997x_edid_cksum(dev, edid_ext, &cksum);
2470  if (err < 0)
2471  return err;
2472 
2473  err = tda1997x_write(dev, EDID_IN_BYTE128, 127, edid_ext);
2474  if (err < 0)
2475  return err;
2476 
2477  /* Write block 1 checksum byte */
2478  err = write_reg(dev, EDID_IN_CHECKSUM1, cksum);
2479  if (err < 0)
2480  return err;
2481 
2482  return 0;
2483 }
tda1997x_edid_cksum
static int tda1997x_edid_cksum(struct tda1997x_dev *dev, uint8_t *edid, uint8_t *cksum)
Calculate EDID Block Checksum.
Definition: tda1997x.c:2409
tda1997x_write
static int tda1997x_write(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t len, uint8_t *data)
Write Data.
Definition: tda1997x.c:1767
write_reg
static int write_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t data)
Write Register.
Definition: tda1997x.c:1849

◆ tda1997x_cfg_prefilter()

int tda1997x_cfg_prefilter ( struct tda1997x_dev *  dev,
enum tda1997x_filters_ctrl_prefil  bu,
enum tda1997x_filters_ctrl_prefil  rv 
)

#include <projects/lib/tda1997x.c>

Configure Prefilter.

Parameters
devTDA1997X device structure pointer
buB/Cb channel prefilter configuration
rvR/Cr channel prefilter configuration
Returns
0 on success, non-zero error status otherwise
2194 {
2195  int err;
2196  uint8_t reg_val = ((uint8_t)bu << 2) | ((uint8_t)rv);
2197 
2198  /* Configure prefilter */
2199  err = write_reg(dev, FILTERS_CTRL, reg_val);
2200  if (err < 0)
2201  return err;
2202 
2203  if ((bu == FILTERS_CTRL_PREFILTER_OFF) && (rv == FILTERS_CTRL_PREFILTER_OFF))
2204  reg_val = VDP_CTRL_PREFILTER_BYPASS;
2205  else
2206  reg_val = 0;
2207 
2208  /* Set or clear prefilter bypass bit */
2209  err = write_reg_mask(dev, VDP_CTRL, VDP_CTRL_PREFILTER_BYPASS, reg_val);
2210  if (err < 0)
2211  return err;
2212 
2213  return 0;
2214 }
write_reg_mask
static int write_reg_mask(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t mask, uint8_t val)
Register Mask Write Write a specified value with specified mask bits to a register.
Definition: tda1997x.c:1866
write_reg
static int write_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t data)
Write Register.
Definition: tda1997x.c:1849

◆ tda1997x_cfg_spa()

static int tda1997x_cfg_spa ( struct tda1997x_dev *  dev,
uint8_t *  edid1,
uint8_t  offset,
uint16_t *  spa 
)
static

#include <projects/lib/tda1997x.c>

Configure Source Physical Address.

Parameters
devTDA1997X device structure pointer
edid1Pointer to start of EDID extension block
offsetOffset of SPA within the EDID extension block
spaPointer to array of SPAs
Returns
0 on success, non-zero error status otherwise
2496 {
2497  int err;
2498  uint8_t reg_val[7];
2499  uint8_t i, tmp = 0;
2500 
2501  if ((dev == NULL) ||
2502  (edid1 == NULL) ||
2503  (spa == NULL))
2504  return (-1);
2505 
2506  /* Build SPA offset and value registers */
2507  reg_val[0] = offset;
2508  reg_val[1] = (uint8_t)(spa[0] >> 8);
2509  reg_val[2] = (uint8_t)(spa[0] & 0xFFU);
2510 
2511  reg_val[4] = (uint8_t)(spa[1] >> 8);
2512  reg_val[5] = (uint8_t)(spa[1] & 0xFFU);
2513 
2514  /* First calculate the EDID block 1 checksum without the SPA bytes */
2515  for (i = 0; i < 127; i++)
2516  if ((i == offset) || (i == (offset + 1)))
2517  continue;
2518  else
2519  tmp += edid1[i];
2520 
2521  /* Add the checksums for the SPAs separately */
2522  reg_val[3] = tmp + (((spa[0] >> 8) + spa[0]) & 0xFFU);
2523  reg_val[6] = tmp + (((spa[1] >> 8) + spa[1]) & 0xFFU);
2524 
2525  /* Calculate 2's complement */
2526  reg_val[3] = (uint8_t)((0xFFU - reg_val[3]) + 1);
2527  reg_val[6] = (uint8_t)((0xFFU - reg_val[6]) + 1);
2528 
2529  err = tda1997x_write(dev, EDID_IN_SPA_SUB, 7, reg_val);
2530  if (err < 0)
2531  return err;
2532 
2533  return 0;
2534 }
tda1997x_write
static int tda1997x_write(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t len, uint8_t *data)
Write Data.
Definition: tda1997x.c:1767

◆ tda1997x_cfg_vid_out()

int tda1997x_cfg_vid_out ( struct tda1997x_dev *  dev)

#include <projects/lib/tda1997x.c>

Configure Video Output Format.

Parameters
devTDA1997X device structure pointer
Returns
0 on success, non-zero error code otherwise
2117 {
2118  int err;
2119 
2120  /* Bypass formatter (not needed in RGB444 with no blanking or timing ref) */
2121  err = write_reg_mask(dev, VDP_CTRL, VDP_CTRL_FORMATTER_BYPASS, 0);
2122  if (err < 0)
2123  return err;
2124 
2125  /* Configure color space conversion (bypass) */
2126  err = tda1997x_cfg_conv(dev, NULL);
2127  if (err < 0)
2128  return err;
2129 
2130  /* Set blanking codes */
2131  err = tda1997x_write(dev, BLK_GY_MSB, 6, (uint8_t *) blank_rgb);
2132  if (err < 0)
2133  return err;
2134 
2135  /* Configure pixel repeater */
2136  err = write_reg_mask(dev, PIX_REPEAT, PIX_REPEAT_UP_SEL_MASK, (uint8_t) PIX_REPEAT_UP_SEL_BYPASS); // PIX_REPEAT_UP_SEL_REPEATCHROMA);
2137  if (err < 0)
2138  return err;
2139 
2140  err = write_reg_mask(dev, PIX_REPEAT, PIX_REPEAT_PIX_REP_MASK, 0);
2141  if (err < 0)
2142  return err;
2143 
2144  /* Configure prefilter */
2145  err = tda1997x_cfg_prefilter(dev, FILTERS_CTRL_PREFILTER_OFF, FILTERS_CTRL_PREFILTER_OFF);
2146  if (err < 0)
2147  return err;
2148 
2149  /* Configure video output */
2150  err = write_reg_mask(dev,
2151  OF_CTRL,
2152  OF_CTRL_BLANKING_INSERT | OF_CTRL_TIMINGREF_INSERT | OF_CTRL_FORMAT_MASK,
2153  OF_CTRL_TIMINGREF_INSERT | (uint8_t) OF_CTRL_FORMAT_444);
2154  if (err < 0)
2155  return err;
2156 
2157  err = write_reg(dev, VHREF_CTRL, 0x16);
2158  if (err < 0)
2159  return err;
2160 
2161  /* Configure pixel clock generator and delay */
2162  err = write_reg_mask(dev, CLKOUT_CTRL, CLKOUT_CLK_DELAY_MASK, 0x30);
2163  if (err < 0)
2164  return err;
2165 
2166  /* Configure DE output signal */
2167  err = write_reg(dev, DE_FREF_SEL, 0x82);
2168  if (err < 0)
2169  return err;
2170 
2171  /* Configure HS output signal */
2172  err = write_reg(dev, HS_HREF_SEL, 0x82);
2173  if (err < 0)
2174  return err;
2175 
2176  /* Configure VS output signal */
2177  err = write_reg(dev, VS_VREF_SEL, 0x82);
2178  if (err < 0)
2179  return err;
2180 
2181  return 0;
2182 }
CLKOUT_CLK_DELAY_MASK
#define CLKOUT_CLK_DELAY_MASK
Definition: tda1997x.c:116
tda1997x_write
static int tda1997x_write(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t len, uint8_t *data)
Write Data.
Definition: tda1997x.c:1767
tda1997x_cfg_conv
int tda1997x_cfg_conv(struct tda1997x_dev *dev, int16_t *mtx)
Configure Colorspace Conversion.
Definition: tda1997x.c:2083
tda1997x_cfg_prefilter
int tda1997x_cfg_prefilter(struct tda1997x_dev *dev, enum tda1997x_filters_ctrl_prefil bu, enum tda1997x_filters_ctrl_prefil rv)
Configure Prefilter.
Definition: tda1997x.c:2193
write_reg_mask
static int write_reg_mask(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t mask, uint8_t val)
Register Mask Write Write a specified value with specified mask bits to a register.
Definition: tda1997x.c:1866
write_reg
static int write_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t data)
Write Register.
Definition: tda1997x.c:1849

◆ tda1997x_cfg_vp()

int tda1997x_cfg_vp ( struct tda1997x_dev *  dev,
uint8_t *  vp_conf 
)

#include <projects/lib/tda1997x.c>

Configure Video Port.

Parameters
devTDA1997X device structure pointer
vp_confPointer to array of video port control values
Returns
0 on success, non-zero error status otherwise
2072 {
2073  return tda1997x_write(dev, VP35_32_CTRL, 9, vp_conf);
2074 }
tda1997x_write
static int tda1997x_write(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t len, uint8_t *data)
Write Data.
Definition: tda1997x.c:1767

◆ tda1997x_clear_irq()

static int tda1997x_clear_irq ( struct tda1997x_dev *  dev,
enum hdmi_reg  reg,
uint8_t *  val 
)
static

#include <projects/lib/tda1997x.c>

Clear Interrupt Register.

Parameters
devTDA1997X device structure pointer
regRegister to clear
valPointer to data to write from register
Returns
0 on success, non-zero error status otherwise
1989 {
1990  int err;
1991  uint8_t tmp;
1992 
1993  err = read_reg(dev, reg, &tmp);
1994  if (err < 0)
1995  return err;
1996 
1997  err = write_reg(dev, reg, tmp);
1998  if (err < 0)
1999  return err;
2000 
2001  *val = tmp;
2002 
2003  return 0;
2004 }
read_reg
static int read_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t *data)
Read Register.
Definition: tda1997x.c:1836
write_reg
static int write_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t data)
Write Register.
Definition: tda1997x.c:1849

◆ tda1997x_edid_cksum()

static int tda1997x_edid_cksum ( struct tda1997x_dev *  dev,
uint8_t *  edid,
uint8_t *  cksum 
)
static

#include <projects/lib/tda1997x.c>

Calculate EDID Block Checksum.

Parameters
devTDA1997X device structure pointer
cksumPointer to data to write checksum value
Returns
None
2410 {
2411  uint8_t i;
2412  uint8_t tmp = 0;
2413  uint8_t *pedid = edid;
2414 
2415  if ((edid == NULL) || (cksum == NULL))
2416  return (-1);
2417 
2418  for (i = 0; i < 127; i++)
2419  tmp += *pedid++;
2420 
2421  /* Write 2's complement to the checksum */
2422  *cksum = (0xFFU - tmp) + 1;
2423 
2424  return 0;
2425 }

◆ tda1997x_get_audio_flags()

int tda1997x_get_audio_flags ( struct tda1997x_dev *  dev,
uint8_t *  status 
)

#include <projects/lib/tda1997x.c>

Get Audio Status.

Parameters
devTDA1997X device structure pointer
statusPointer to audio status to write value
Returns
0 on success, non-zero error status otherwise
2334 {
2335  return read_reg(dev, AUDIO_FLAGS, status);
2336 }
read_reg
static int read_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t *data)
Read Register.
Definition: tda1997x.c:1836

◆ tda1997x_get_audio_freq()

int tda1997x_get_audio_freq ( struct tda1997x_dev *  dev,
enum tda1997x_audio_freq *  freq 
)

#include <projects/lib/tda1997x.c>

Get Audio Frequency.

Parameters
devTDA1997X device structure pointer
freqPointer to frequency to write value
Returns
0 on success, non-zero error status otherwise
2347 {
2348  int err;
2349  uint8_t reg_val;
2350 
2351  err = read_reg(dev, AUDIO_FREQ, &reg_val);
2352  if (err < 0)
2353  return err;
2354 
2355  *freq = (enum tda1997x_audio_freq)reg_val;
2356 
2357  return 0;
2358 }
read_reg
static int read_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t *data)
Read Register.
Definition: tda1997x.c:1836

◆ tda1997x_get_chan_status()

int tda1997x_get_chan_status ( struct tda1997x_dev *  dev)

#include <projects/lib/tda1997x.c>

Get Audio Channel Status.

Parameters
devTDA1997X device structure pointer
Returns
0 on success, non-zero error status otherwise
2368 {
2369  int err;
2370  uint8_t reg_val[12];
2371 
2372  err = tda1997x_read(dev, CH_STAT_BYTE0, 12, reg_val);
2373  if (err < 0)
2374  return err;
2375 
2376  return 0;
2377 }
tda1997x_read
static int tda1997x_read(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t len, uint8_t *data)
Read Data.
Definition: tda1997x.c:1804

◆ tda1997x_get_timing()

int tda1997x_get_timing ( struct tda1997x_dev *  dev,
uint8_t *  data 
)

#include <projects/lib/tda1997x.c>

Get Timing Values Sets an data memory block to the video timing register values.

Parameters
devTDA1997X device structure pointer
0on success, non-zero error status otherwise
2639 {
2640  int ret;
2641 
2642  ret = tda1997x_read(dev, V_PER_MSB, 26, data);
2643 
2644  data += 26;
2645 
2646  ret = tda1997x_read(dev, PXCNT_PR_MSB, 48, data);
2647  if (ret < 0)
2648  return ret;
2649 
2650  return 0;
2651 }
tda1997x_read
static int tda1997x_read(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t len, uint8_t *data)
Read Data.
Definition: tda1997x.c:1804

◆ tda1997x_handle_irq()

int tda1997x_handle_irq ( struct tda1997x_dev *  dev)

#include <projects/lib/tda1997x.c>

Handle TDA1997x Interrupt.

Parameters
devTDA1997X device structure pointer
Returns
0 on success, non-zero error status otherwise
3347 {
3348  int err;
3349  uint8_t irq_flags_top, reg_val;
3350  uint8_t status;
3351 
3352  do {
3353  /* Read top level flags */
3354  err = read_reg(dev, IRQ_FLG_CLR_TOP, &irq_flags_top);
3355  if (err < 0)
3356  return err;
3357 
3358  /* Start-up sequence source handling */
3359  if (irq_flags_top & IRQ_TOP_SUS) {
3360  /* Read the SUS interrupt flags register and clear */
3361  err = tda1997x_clear_irq(dev, IRQ_FLG_CLR_SUS, &reg_val);
3362  if (err < 0)
3363  return err;
3364 
3365  err = tda1997x_sus_irq(dev, reg_val);
3366  if (err < 0)
3367  return err;
3368  }
3369 
3370  if (irq_flags_top & IRQ_TOP_RATE) {
3371  err = tda1997x_clear_irq(dev, IRQ_FLG_CLR_RATE, &reg_val);
3372  if (err < 0)
3373  return err;
3374 
3375  if (reg_val & IRQ_RATE_RXDA) {
3376  /* Read interrupt status registers */
3377  err = read_reg(dev, CLK_A_STATUS, &status);
3378  if (err < 0)
3379  return err;
3380 
3381  err = read_reg(dev, CLK_B_STATUS, &status);
3382  if (err < 0)
3383  return err;
3384 
3385  err = read_reg(dev, SUS_STATUS, &status);
3386  if (err < 0)
3387  return err;
3388  }
3389  }
3390 
3391  if (irq_flags_top & IRQ_TOP_MODE) {
3392  err = tda1997x_clear_irq(dev, IRQ_FLG_CLR_MODE, &reg_val);
3393  if (err < 0)
3394  return err;
3395 
3396  if (reg_val & IRQ_MODE_FLAGS) {
3397  err = read_reg(dev, HDMI_FLAGS, &status);
3398  if (err < 0)
3399  return err;
3400 
3401 // if (status & (HDMI_FLAGS_AUD_FIFO_OVR | HDMI_FLAGS_AUD_FIFO_LOW)) {
3402 // err = tda1997x_audio_fifo_rst(dev);
3403 // if (err < 0)
3404 // return err;
3405 // }
3406  }
3407  }
3408 
3409  /* Infoframe interrupt source handling */
3410  if (irq_flags_top & IRQ_TOP_INFO) {
3411  /* Read the infoframe interrupt flags register and clear */
3412  err = tda1997x_clear_irq(dev, IRQ_FLG_CLR_INFO, &reg_val);
3413  if (err < 0)
3414  return err;
3415 
3416  err = tda1997x_infoframe_irq(dev, reg_val);
3417  if (err < 0)
3418  return err;
3419  }
3420 
3421  /* Audio interrupt source handling */
3422  if (irq_flags_top & IRQ_TOP_AUDIO) {
3423  /* Read the audio interrupt flags register and clear */
3424  err = tda1997x_clear_irq(dev, IRQ_FLG_CLR_AUDIO, &reg_val);
3425  if (err < 0)
3426  return err;
3427 
3428  err = tda1997x_audio_irq(dev, reg_val);
3429  if (err < 0)
3430  return err;
3431  }
3432 
3433  /* AFE interrupt source handling */
3434  if (irq_flags_top & IRQ_TOP_AFE) {
3435  err = tda1997x_clear_irq(dev, IRQ_FLG_CLR_AFE, &reg_val);
3436  if (err < 0)
3437  return err;
3438 
3439  err = tda1997x_afe_irq(dev, reg_val);
3440  if (err < 0)
3441  return err;
3442  }
3443  } while (irq_flags_top != 0);
3444 
3445  return 0;
3446 }
tda1997x_clear_irq
static int tda1997x_clear_irq(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t *val)
Clear Interrupt Register.
Definition: tda1997x.c:1988
tda1997x_afe_irq
int tda1997x_afe_irq(struct tda1997x_dev *dev, uint8_t flags)
AFE Interrupt Handler.
Definition: tda1997x.c:3334
read_reg
static int read_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t *data)
Read Register.
Definition: tda1997x.c:1836
tda1997x_infoframe_irq
static int tda1997x_infoframe_irq(struct tda1997x_dev *dev, uint8_t flags)
Parse Infoframe.
Definition: tda1997x.c:3207
tda1997x_audio_irq
int tda1997x_audio_irq(struct tda1997x_dev *dev, uint8_t flags)
Audio Interrupt Handler.
Definition: tda1997x.c:3250
tda1997x_sus_irq
static int tda1997x_sus_irq(struct tda1997x_dev *dev, uint8_t flags)
Startup Sequence Interrupt Handler.
Definition: tda1997x.c:3081

◆ tda1997x_info_rst()

static int tda1997x_info_rst ( struct tda1997x_dev *  dev,
uint8_t  rst 
)
static

#include <projects/lib/tda1997x.c>

Infoframe Reset.

Parameters
devTDA1997X device structure pointer
info_rstInfoframe reset bitfield
sus_enStart up sequence enabled
Returns
0 on success, non-zero error status otherwise
2027 {
2028  int err;
2029  uint8_t reg_val;
2030 
2031  err = write_reg_mask(dev, HDMI_INFO_RST, rst, rst);
2032  if (err < 0)
2033  return err;
2034 
2035  err = write_reg_mask(dev, HDMI_INFO_RST, rst, 0);
2036  if (err < 0)
2037  return err;
2038 
2039  /* Clear interrupts if infoframes have been reset */
2040  if (rst & INFO_RST_INFOFRAME) {
2041  err = tda1997x_clear_irq(dev, IRQ_FLG_CLR_MODE, &reg_val);
2042  if (err < 0)
2043  return err;
2044  }
2045 
2046  return 0;
2047 }
INFO_RST_INFOFRAME
#define INFO_RST_INFOFRAME
Definition: tda1997x.c:90
tda1997x_clear_irq
static int tda1997x_clear_irq(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t *val)
Clear Interrupt Register.
Definition: tda1997x.c:1988
write_reg_mask
static int write_reg_mask(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t mask, uint8_t val)
Register Mask Write Write a specified value with specified mask bits to a register.
Definition: tda1997x.c:1866

◆ tda1997x_infoframe_irq()

static int tda1997x_infoframe_irq ( struct tda1997x_dev *  dev,
uint8_t  flags 
)
static

#include <projects/lib/tda1997x.c>

Parse Infoframe.

Parameters
devTDA1997X device structure pointer
flagsFlags read from interrupt flags register
Returns
0 on success, non-zero error status otherwise
3208 {
3209  int err;
3210  uint8_t i;
3211  uint8_t reg_val;
3212  enum hdmi_reg reg = VS_IF_HDMI_UPDATE;
3213  union tda1997x_infoframe info;
3214 
3215  for (i = 0; i < NIRQ_SOURCE_FLAGS; i++) {
3216  /* Check if interrupt flag is set */
3217  if (flags & (1 << i)) {
3218 
3219  /* Check the update register */
3220  err = read_reg(dev, reg, &reg_val);
3221  if (err < 0)
3222  return err;
3223 
3224  /* Read the infoframe if updated (start from infoframe type register) */
3225 // if (reg_val) {
3226  err = tda1997x_read_infoframe(dev, reg + 1, &info);
3227  if (err < 0)
3228  return err;
3229 
3230 // err = tda1997x_parse_infoframe(dev, &info);
3231 // if (err < 0)
3232 // return err;
3233 // }
3234  }
3235 
3236  reg += 32; /* Go to next infoframe update register */
3237  }
3238 
3239  return 0;
3240 }
tda1997x_infoframe
Definition: tda1997x.c:1578
read_reg
static int read_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t *data)
Read Register.
Definition: tda1997x.c:1836
tda1997x_read_infoframe
static int tda1997x_read_infoframe(struct tda1997x_dev *dev, enum hdmi_reg reg, union tda1997x_infoframe *info)
Read Infoframe.
Definition: tda1997x.c:2546

◆ tda1997x_init()

int tda1997x_init ( struct tda1997x_dev *  dev,
struct tda1997x_cfg *  cfg,
uint8_t *  edid_block,
uint8_t *  edid_ext 
)

#include <projects/lib/tda1997x.c>

Initialize TDA1997x HDMI Receiver.

Parameters
devTDA1997X device structure pointer
cfgTDA1997X configuration structure pointer to use for initialization
Returns
0 on success, non-zero error status otherwise

< HDCP key decryption seed


Todo:
HDCP configuration and activation
Todo:
Configure video output with structure data

Configure audio

Todo:
Pass audio configuration data to tda1997x_cfg_audio_fmt
2663 {
2664  int err;
2665  uint8_t i, reg_val, mask;
2666  uint16_t hdcp_kds;
2668  if ((dev == NULL) || (cfg == NULL))
2669  return -1;
2670 
2671  dev->cfg = cfg; /* Attach configuration to receiver */
2672  dev->cfg->cur_page = PAGE_INVALID; /* Force initial read/write to set page */
2673 
2674  /* Open the device and perform basic initialization */
2675 
2676  /* Apply WA to get correct I2C access to Rx HDMI*/
2677  err = write_reg(dev, MAN_SUS_HDMI_SEL, MAN_SUS_HDMI_DIS_HDCP | MAN_SUS_HDMI_RST_HDCP);
2678  if (err < 0)
2679  return err;
2680 
2681  err = write_reg(dev, MAN_SUS_HDMI_SEL, 0x00);
2682  if (err < 0)
2683  return err;
2684 
2685  err = write_reg(dev, VDP_CTRL, 0x1f);
2686  if (err < 0)
2687  return err;
2688 
2689 // /* Read and store CEC slave address */
2690 // err = read_reg(dev, SLAVE_ADDR, &reg_val);
2691 // if (err < 0)
2692 // return err;
2693 //
2694 // /* Update CEC address if necessary */
2695 // if ((uint8_t)((reg_val >> 4) & 0x03) != (dev->cfg->cec_addr & 0x03)) {
2696 // err = write_reg_mask(dev, SLAVE_ADDR, 0x30, (uint8_t)((dev->cfg->cec_addr << 4) & 0x30));
2697 // if (err < 0)
2698 // return err;
2699 // }
2700 
2701  /* Disable HPD */
2702  err = write_reg(dev, HPD_AUTO_CTRL, HPD_AUTO_UNSEL);
2703  if (err < 0)
2704  return err;
2705 
2706  /* Wrap these consecutive register writes */
2707  err = write_reg(dev, SUS_SET_RGB2, 0x06);
2708  if (err < 0)
2709  return err;
2710 
2711  err = write_reg(dev, SUS_SET_RGB3, 0x06);
2712  if (err < 0)
2713  return err;
2714 
2715  err = write_reg(dev, RT_MAN_CTRL, 0x43);
2716  if (err < 0)
2717  return err;
2718 
2719  err = write_reg(dev, OF_CTRL, 0x40);
2720  if (err < 0)
2721  return err;
2722 
2723  /* Begin CEC */
2724  /* Enable sync measurement timing */
2725  err = cec_write_reg(dev, PWR_CONTROL, 0x04);
2726  if (err < 0)
2727  return err;
2728 
2729  /* Adjust CEC clock divider */
2730  err = cec_write_reg(dev, OSC_DIVIDER, 0x03);
2731  if (err < 0)
2732  return err;
2733 
2734  err = cec_write_reg(dev, EN_OSC_PERIOD_LSB, 0xA0);
2735  if (err < 0)
2736  return err;
2737  /* End CEC */
2738 
2739  err = write_reg(dev, TIMER_D, 0x54);
2740  if (err < 0)
2741  return err;
2742  /*
2743  * Enable power switch - SRAM content is always valid
2744  * (in case E-MTP is not or mis-programmed)
2745  */
2746  err = cec_write_reg_mask(dev, CONTROL, 0x20, 0x20);
2747  if (err < 0)
2748  return err;
2749 
2750  usleep(1000 * 50); /* Short delay to allow power to settle */
2751 
2752  /* Initialize top level interrupts */
2753  err = write_reg(dev,
2754  IRQ_MASK_TOP,
2755  IRQ_TOP_SUS |
2756  IRQ_TOP_RATE |
2757  IRQ_TOP_MODE |
2758  IRQ_TOP_INFO |
2759  IRQ_TOP_AUDIO |
2760  IRQ_TOP_HDCP);
2761  if (err < 0)
2762  return err;
2763 
2764  err = write_reg(dev, IRQ_MASK_SUS, IRQ_SUS_MTP | IRQ_SUS_FORMAT | IRQ_SUS_END);
2765  if (err < 0)
2766  return err;
2767 
2768  /* Enable rate stability change interrupts for input */
2769  err = write_reg(dev, IRQ_MASK_RATE, IRQ_RATE_RXDA);
2770  if (err < 0)
2771  return err;
2772 
2773  /* Enable interrupts for audio, SPD, and AVI infoframes */
2774  err = write_reg(dev, IRQ_MASK_INFO, IRQ_INFO_AUD | IRQ_INFO_SPD | IRQ_INFO_AVI);
2775  if (err < 0)
2776  return err;
2777 
2778  /* Enable audio interrupts */
2779  err = write_reg(dev,
2780  IRQ_MASK_AUDIO,
2781  IRQ_AUDIO_FIFO_ERROR |
2782  IRQ_AUDIO_FIFO_UNMUTE |
2783  IRQ_AUDIO_CHAN_STATUS |
2784  IRQ_AUDIO_MUTE |
2785  IRQ_AUDIO_FLAGS |
2786  IRQ_AUDIO_FREQ_CHANGE);
2787  if (err < 0)
2788  return err;
2789 
2790  /* Enable HDCP interrupts */
2791  err = write_reg(dev, IRQ_MASK_HDCP, IRQ_HDCP_STATE_C5);
2792  if (err < 0)
2793  return err;
2794 
2795  /* Enable mode interrupts */
2796  err = write_reg(dev, IRQ_MASK_MODE, IRQ_MODE_FLAGS);
2797  if (err < 0)
2798  return err;
2799 
2800  for (i = 0; i < 9; i++) {
2801  /* Clear pending top level interrupts */
2802  err = write_reg(dev, IRQ_FLG_CLR_TOP + i, 0xff);
2803  if (err < 0)
2804  return err;
2805  }
2806 
2807  /* Initialize TMDS */
2808  err = tda1997x_write(dev, CLK_MIN_RATE_MSB, 6, (uint8_t *) clk_rate);
2809  if (err < 0)
2810  return err;
2811 
2812  /* Deep color filter */
2813  err = write_reg(dev, DEEP_COLOR_CTRL, 0x31);
2814  if (err < 0)
2815  return err;
2816 
2817  /* Disable test pattern */
2818  err = write_reg(dev, SERVICE_MODE, 0x00);
2819  if (err < 0)
2820  return err;
2821 
2822  err = write_reg(dev, INFO_CTRL, 0xff);
2823  if (err < 0)
2824  return err;
2825 
2826  err = write_reg(dev, INFO_EXCEED, 0x03);
2827  if (err < 0)
2828  return err;
2829 
2830  /* No HDCP acknowledge when disabled, reset startup sequence */
2831  err = tda1997x_info_rst(dev, INFO_RST_NACK_HDCP);
2832  if (err < 0)
2833  return err;
2834 
2835  /* Reset startup sequence if indicated */
2836  err = tda1997x_sus_en(dev, 0);
2837  if (err < 0)
2838  return err;
2839 
2840  /* Mute video port on start */
2841  err = tda1997x_cfg_vp(dev, vp_conf_mute);
2842  if (err < 0)
2843  return err;
2844 
2845  /* MTP start read */
2846  /* Clear HDCP download MTP flag to start reading */
2847  err = write_reg_mask(dev, IRQ_FLG_CLR_HDCP, IRQ_HDCP_DLMTP, IRQ_HDCP_DLMTP);
2848  if (err < 0)
2849  return err;
2850 
2851  /* Download MTP into SRAM */
2852  err = write_reg(dev, HMTP_CTRL, HMTP_CNTRL_DL_ALL);
2853  if (err < 0)
2854  return err;
2855 
2856  /* Check HDCP flag INT_FLG_CLR_HDCP_DLMTP */
2857  do {
2858  err = read_reg(dev, IRQ_FLG_CLR_HDCP, &reg_val);
2859  if (err < 0)
2860  return err;
2861  } while ((reg_val & IRQ_HDCP_DLMTP) != IRQ_HDCP_DLMTP);
2862 
2863  /* Get HDCP seed */
2864  err = read_reg(dev, MTP_SEED_INDEX, &reg_val);
2865  if (err < 0)
2866  return err;
2867 
2868  /* Search the seed table for the index value */
2869  for (i = 0; i < TDA1997X_SEED_TABLE_LEN; i++) {
2870  if ((hdcp_seed_tab[i].seed == 0) && (hdcp_seed_tab[i].lookup == 0))
2871  break;
2872 
2873  if (hdcp_seed_tab[i].lookup == (uint16_t)reg_val) {
2874  /* Store the encryption key seed */
2875  hdcp_kds = hdcp_seed_tab[i].seed;
2876  break;
2877  }
2878  }
2879 
2880  /* Disable HDCP */
2881  err = write_reg(dev, HDCP_CTRL, HDCP_CTRL_DECRYPTKEY_ON);
2882  if (err < 0)
2883  return err;
2884 
2885  /* Write key decryption seed MSB */
2886  err = write_reg(dev, HDCP_KDS_MSB, (uint8_t)(hdcp_kds >> 8));
2887  if (err < 0)
2888  return err;
2889 
2890  /* Write key decryption seed LSB */
2891  err = write_reg(dev, HDCP_KDS_LSB, (uint8_t)(hdcp_kds & 0xFF));
2892  if (err < 0)
2893  return err;
2894 
2895  /* Set the HDCP DDC address */
2896  err = write_reg(dev, HDCP_DDC_ADDR, TDA1997X_HDCP_DDC_ADDR);
2897  if (err < 0)
2898  return err;
2899 
2900  /* Clear HDCP interrupt status bits that may have been raised during this process */
2901  err = tda1997x_clear_irq(dev, IRQ_FLG_CLR_HDCP, &reg_val);
2902  if (err < 0)
2903  return err;
2904 
2905  /* THE DEVICE IS INITIALIZED AT THIS POINT */
2906 
2907  /* Set HPD low */
2908  err = write_reg_mask(dev, HPD_POWER, HPD_POWER_BYPASS_MASK, 0);
2909  if (err < 0)
2910  return err;
2911 
2912  /* Set HPD low */
2913  err = write_reg_mask(dev, HPD_MAN_CTRL, HPD_MAN_GAIN_MASK, 0);
2914  if (err < 0)
2915  return err;
2916 
2917  err = write_reg(dev, HDCP_BCAPS, HDCP_BCAPS_DEFAULT | HDCP_BCAPS_FAST_REAUTH);
2918  if (err < 0)
2919  return err;
2920 
2921  /* Configure HDMI */
2922  err = write_reg_mask(dev,
2923  HDMI_CTRL,
2924  HDMI_CTRL_HDCP_MASK | HDMI_CTRL_MUTE_MASK,
2925  (uint8_t) HDMI_CTRL_MUTE_OFF | (uint8_t) HDMI_CTRL_HDCP_AUTO);
2926  if (err < 0)
2927  return err;
2928 
2929  /* EDID Nack OFF */
2930  err = write_reg_mask(dev, EDID_ENABLE, 0x83, 0x83);
2931  if (err < 0)
2932  return err;
2933 
2937  /* 1. Enable HDCP NACK */
2938  err = write_reg_mask(dev, HDMI_INFO_RST, INFO_RST_NACK_HDCP, INFO_RST_NACK_HDCP);
2939  if (err < 0)
2940  return err;
2941 
2942  /* 2. Disable HDCP */
2943 
2944  /* 3. Set private key index */
2945 
2946  usleep(1000 * 20);
2947 
2948  /* 4. Disable HDCP NACK */
2949  err = write_reg_mask(dev, HDMI_INFO_RST, INFO_RST_NACK_HDCP, 0);
2950  if (err < 0)
2951  return err;
2952 
2953  /* 5. Configure HDCP error protection */
2954 
2955  /* Reset SUS to force format detection */
2956  err = tda1997x_sus_en(dev, 0);
2957  if (err < 0)
2958  return err;
2959 
2960  err = tda1997x_sus_en(dev, SUS_ENABLE);
2961  if (err < 0)
2962  return err;
2963 
2964  err = write_reg_mask(dev, HPD_AUTO_CTRL, HPD_AUTO_OTHER, HPD_AUTO_OTHER);
2965  if (err < 0)
2966  return err;
2967 
2968  err = tda1997x_cfg_edid(dev, edid_block, edid_ext);
2969  if (err < 0)
2970  return err;
2971 
2972  err = tda1997x_cfg_spa(dev, &edid_block[128], 8, spa_edid);
2973  if (err < 0)
2974  return err;
2975 
2976  /* Load EDID configuration data */
2977  err = tda1997x_write(dev, EDID_IN_VERSION, 8, ddc_config);
2978  if (err < 0)
2979  return err;
2980 
2981  err = tda1997x_write(dev, RT_AUTO_CTRL, 6, rt_config);
2982  if (err < 0)
2983  return err;
2984 
2985  err = write_reg_mask(dev, HPD_POWER, HPD_POWER_BYPASS_MASK, 0x04);
2986  if (err < 0)
2987  return err;
2988 
2989  err = write_reg(dev, INPUT_SEL, 0x00);
2990  if (err < 0)
2991  return err;
2992 
2993 // /* Configure HDCP without resetting SUS */
2994 // err = tda1997x_info_rst(dev, INFO_RST_NACK_HDCP, SUS_ENABLE);
2995 // if (err < 0)
2996 // return err;
2997 
2998  /* Enable HDCP Nack */
2999 
3000  /* Disable HDCP */
3001 
3002  /* Index the private key */
3003 
3004  /* Encrypted, enable HDCP */
3005 
3006  /* Enable HDCP acknowledge when HDCP is enabled */
3007 
3008  /* Configure HDCP error protection */
3009  mask = INPUT_SEL_VDPR_FMT_MASK | INPUT_SEL_HDMIOUT;
3010  err = write_reg_mask(dev, INPUT_SEL, mask, INPUT_SEL_FORMAT_RESET);
3011  if (err < 0)
3012  return err;
3013 
3014  /* Mute output */
3015  mask = OF_CTRL_OUTPUT_ACTIVE | OF_CTRL_VIDEO_HIZ;
3016  err = write_reg_mask(dev, OF_CTRL, mask, OF_CTRL_VIDEO_HIZ);
3017  if (err < 0)
3018  return err;
3019 
3023  err = tda1997x_cfg_vid_out(dev);
3024  if (err < 0)
3025  return err;
3026 
3027  /* Define video port */
3028  err = tda1997x_cfg_vp(dev, vp_conf444);
3029  if (err < 0)
3030  return err;
3031 
3032  /* Unmute output */
3033  err = write_reg_mask(dev, OF_CTRL, OF_CTRL_OUTPUT_ACTIVE | OF_CTRL_VIDEO_HIZ, OF_CTRL_OUTPUT_ACTIVE);
3034  if (err < 0)
3035  return err;
3036 
3041  err = tda1997x_cfg_audio_fmt(dev);
3042  if (err < 0)
3043  return err;
3044 
3045  /* Reset infoframes */
3046  err = tda1997x_info_rst(dev, INFO_RST_AI);
3047  if (err < 0)
3048  return err;
3049 
3050  err = tda1997x_info_rst(dev, INFO_RST_INFOFRAME);
3051  if (err < 0)
3052  return err;
3053 
3054  err = tda1997x_info_rst(dev, INFO_RST_AUDIO);
3055  if (err < 0)
3056  return err;
3057 
3058  err = tda1997x_info_rst(dev, INFO_RST_GAMUT);
3059  if (err < 0)
3060  return err;
3061 
3062  err = tda1997x_sus_en(dev, SUS_ENABLE);
3063  if (err < 0)
3064  return err;
3065 
3066  err = read_reg(dev, HDMI_FLAGS, &reg_val);
3067  if (err < 0)
3068  return err;
3069 
3070  return 0;
3071 }
tda1997x_info_rst
static int tda1997x_info_rst(struct tda1997x_dev *dev, uint8_t rst)
Infoframe Reset.
Definition: tda1997x.c:2026
tda1997x_sus_en
static int tda1997x_sus_en(struct tda1997x_dev *dev, uint8_t en)
Enable Startup Sequence.
Definition: tda1997x.c:2056
tda1997x_cfg_spa
static int tda1997x_cfg_spa(struct tda1997x_dev *dev, uint8_t *edid1, uint8_t offset, uint16_t *spa)
Configure Source Physical Address.
Definition: tda1997x.c:2495
cec_write_reg_mask
static int cec_write_reg_mask(struct tda1997x_dev *dev, enum cec_reg reg, uint8_t mask, uint8_t val)
CEC Register Mask Write Write a specified value with specified mask bits to a register.
Definition: tda1997x.c:1965
INFO_RST_AI
#define INFO_RST_AI
Definition: tda1997x.c:89
INFO_RST_INFOFRAME
#define INFO_RST_INFOFRAME
Definition: tda1997x.c:90
tda1997x_cfg_edid
int tda1997x_cfg_edid(struct tda1997x_dev *dev, uint8_t *edid, uint8_t *edid_ext)
Configure EDID.
Definition: tda1997x.c:2437
tda1997x_clear_irq
static int tda1997x_clear_irq(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t *val)
Clear Interrupt Register.
Definition: tda1997x.c:1988
cec_write_reg
static int cec_write_reg(struct tda1997x_dev *dev, enum cec_reg reg, uint8_t data)
CEC Write Register.
Definition: tda1997x.c:1935
INFO_RST_GAMUT
#define INFO_RST_GAMUT
Definition: tda1997x.c:88
tda1997x_cfg_vp
int tda1997x_cfg_vp(struct tda1997x_dev *dev, uint8_t *vp_conf)
Configure Video Port.
Definition: tda1997x.c:2071
OF_CTRL_OUTPUT_ACTIVE
#define OF_CTRL_OUTPUT_ACTIVE
Definition: tda1997x.c:109
read_reg
static int read_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t *data)
Read Register.
Definition: tda1997x.c:1836
tda1997x_write
static int tda1997x_write(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t len, uint8_t *data)
Write Data.
Definition: tda1997x.c:1767
OF_CTRL_VIDEO_HIZ
#define OF_CTRL_VIDEO_HIZ
Definition: tda1997x.c:110
write_reg_mask
static int write_reg_mask(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t mask, uint8_t val)
Register Mask Write Write a specified value with specified mask bits to a register.
Definition: tda1997x.c:1866
tda1997x_cfg_audio_fmt
int tda1997x_cfg_audio_fmt(struct tda1997x_dev *dev)
Configure Audio Format.
Definition: tda1997x.c:2223
INFO_RST_NACK_HDCP
#define INFO_RST_NACK_HDCP
Definition: tda1997x.c:82
tda1997x_cfg_vid_out
int tda1997x_cfg_vid_out(struct tda1997x_dev *dev)
Configure Video Output Format.
Definition: tda1997x.c:2116
INFO_RST_AUDIO
#define INFO_RST_AUDIO
Definition: tda1997x.c:91
write_reg
static int write_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t data)
Write Register.
Definition: tda1997x.c:1849

◆ tda1997x_parse_aud_infoframe()

int tda1997x_parse_aud_infoframe ( struct tda1997x_dev *  dev,
struct tda1997x_info_aud *  info 
)

#include <projects/lib/tda1997x.c>

Parse Audio Infoframe.

Parameters
devTDA1997X device structure pointer
infoPointer to audio infoframe structure
Returns
0 on success, non-zero error status otherwise
2602 {
2603  int err;
2604 
2605  /* Set the audio output based to match the infoframe */
2606  err = write_reg(dev, AUDIO_PATH, info->chan_alloc);
2607  if (err < 0)
2608  return err;
2609 
2610  /* Reset the audio FIFO */
2611  err = tda1997x_audio_fifo_rst(dev);
2612  if (err < 0)
2613  return err;
2614 
2615  return 0;
2616 }
tda1997x_info_aud::chan_alloc
uint8_t chan_alloc
Definition: tda1997x.c:1565
tda1997x_audio_fifo_rst
static int tda1997x_audio_fifo_rst(struct tda1997x_dev *dev)
Reset Audio FIFO.
Definition: tda1997x.c:2386
write_reg
static int write_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t data)
Write Register.
Definition: tda1997x.c:1849

◆ tda1997x_parse_infoframe()

int tda1997x_parse_infoframe ( struct tda1997x_dev *  dev,
union tda1997x_infoframe *  info 
)

#include <projects/lib/tda1997x.c>

Parse Infoframe.

Parameters
devTDA1997X device structure pointer
infoPointer to infoframe union data
Returns
0 on success, non-zero error status otherwise
2589 {
2590  return 0;
2591 }

◆ tda1997x_print_infoframe()

int tda1997x_print_infoframe ( struct tda1997x_dev *  dev)

#include <projects/lib/tda1997x.c>

Print Infoframe.

Parameters
devTDA1997X device structure pointer
Returns
0 on success, non-zero error status otherwise
2626 {
2627  return 0;
2628 }

◆ tda1997x_read()

static int tda1997x_read ( struct tda1997x_dev *  dev,
enum hdmi_reg  reg,
uint8_t  len,
uint8_t *  data 
)
static

#include <projects/lib/tda1997x.c>

Read Data.

Parameters
devTDA1997X device structure pointer
regStart register and page address
lenLength of data to read from device
dataPointer to data to read to
Returns
Number of bytes read or less-than-zero error status
1805 {
1806  int i, err;
1807  struct tda1997x_cfg *cfg = dev->cfg;
1808  uint8_t page = PAGE_OF(reg);
1809 
1810  if (dev->cfg->cur_page != page) {
1811  /* Change the page */
1812  err = cfg->i2c_write(cfg->i2c_addr, (uint8_t)CURPAGE, &page);
1813  if (err < 0)
1814  return err;
1815 
1816  dev->cfg->cur_page = page;
1817  }
1818 
1819  for (i = 0; i < len; i++, data++) {
1820  err = cfg->i2c_read(cfg->i2c_addr, (uint8_t)reg + i, data);
1821  if (err < 0)
1822  return err;
1823  }
1824 
1825  return i;
1826 }
tda1997x_cfg
TDA1997X driver configuration.
Definition: tda1997x.h:138

◆ tda1997x_read_infoframe()

static int tda1997x_read_infoframe ( struct tda1997x_dev *  dev,
enum hdmi_reg  reg,
union tda1997x_infoframe *  info 
)
static

#include <projects/lib/tda1997x.c>

Read Infoframe.

Parameters
devTDA1997X device structure pointer
Returns
0 on success, non-zero error status otherwise
2547 {
2548  int err;
2549  uint8_t head[4];
2550  uint8_t *data;
2551 
2552  if ((dev == NULL) || (info == NULL))
2553  return (-1);
2554 
2555  /* Read the infoframe header to determine the type and length */
2556  err = tda1997x_read(dev, reg, 4, head);
2557  if (err < 0)
2558  return err;
2559 
2560  /* Parse the header to determine */
2561  info->any.type = head[0];
2562  info->any.version = head[1];
2563  info->any.len = head[2];
2564  info->any.cksum = head[3];
2565 
2566  /* If invalid type, don't bother reading data */
2567  if ((info->any.type < INFOFRAME_TYPE_VENDOR) || (info->any.type > INFOFRAME_TYPE_MPS))
2568  return (0);
2569 
2570  if ((info->any.len > 0) && (info->any.len <= 27)) {
2571  data = info->any.data;
2572  err = tda1997x_read(dev, reg + 4, info->any.len, data);
2573  if (err < 0)
2574  return err;
2575  }
2576 
2577  return 0;
2578 }
tda1997x_info_any::len
uint8_t len
Definition: tda1997x.c:1497
tda1997x_info_any::data
uint8_t data[27]
Definition: tda1997x.c:1499
tda1997x_info_any::cksum
uint8_t cksum
Definition: tda1997x.c:1498
tda1997x_infoframe::any
struct tda1997x_info_any any
Definition: tda1997x.c:1579
tda1997x_read
static int tda1997x_read(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t len, uint8_t *data)
Read Data.
Definition: tda1997x.c:1804
tda1997x_info_any::version
uint8_t version
Definition: tda1997x.c:1496
tda1997x_info_any::type
enum info_type type
Definition: tda1997x.c:1495

◆ tda1997x_soft_rst()

static int tda1997x_soft_rst ( struct tda1997x_dev *  dev,
uint8_t  rst 
)
static

#include <projects/lib/tda1997x.c>

Software Reset.

Parameters
devTDA1997X device structure pointer
rstReset (> 0) or enable (0)
Returns
0 on success, non-zero error status otherwise
2014 {
2015  return write_reg(dev, HDMI_SOFT_RST, rst);
2016 }
write_reg
static int write_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t data)
Write Register.
Definition: tda1997x.c:1849

◆ tda1997x_sus_en()

static int tda1997x_sus_en ( struct tda1997x_dev *  dev,
uint8_t  en 
)
static

#include <projects/lib/tda1997x.c>

Enable Startup Sequence.

Parameters
devTDA1997x device structure pointer
enEnable (> 0) or disable (0)
Returns
0 on success, non-zero error status otherwise
2057 {
2058  if (en)
2059  return write_reg_mask(dev, RATE_CTRL, SUS_ENABLE, SUS_ENABLE);
2060  else
2061  return write_reg_mask(dev, RATE_CTRL, SUS_ENABLE, 0);
2062 }
write_reg_mask
static int write_reg_mask(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t mask, uint8_t val)
Register Mask Write Write a specified value with specified mask bits to a register.
Definition: tda1997x.c:1866

◆ tda1997x_sus_irq()

static int tda1997x_sus_irq ( struct tda1997x_dev *  dev,
uint8_t  flags 
)
static

#include <projects/lib/tda1997x.c>

Startup Sequence Interrupt Handler.

Parameters
devTDA1997X device structure pointer
flagsFlags read from the interrupt flags register
Returns
0 on success, non-zero error status otherwise
3082 {
3083  int err;
3084  uint8_t i, status;
3085 
3086  if (flags & IRQ_SUS_STATE) {
3087  /* SUS state changed */
3088  }
3089 
3090  if (flags & IRQ_SUS_INPUT) {
3091  /* Selected input changed */
3092  }
3093 
3094  if (flags & IRQ_SUS_ACTIVITY) {
3095  /* Activity of selected input changed */
3096  }
3097 
3098  if (flags & IRQ_SUS_END) {
3099 
3100  /* Reset the audio FIFO */
3101  err = tda1997x_audio_fifo_rst(dev);
3102  if (err < 0)
3103  return err;
3104 
3105  err = read_reg(dev, SUS_STATUS, &status);
3106  if (err < 0)
3107  return err;
3108 
3109  if ((status & SUS_STATUS_STATE_MASK) == SUS_STATUS_LAST_STATE) {
3110 
3111  err = read_reg(dev, GAIN_OVR_EN, &status);
3112  if (err < 0)
3113  return err;
3114 
3115  /* Gain mode manual */
3116  if (status == 0x01U) {
3117 
3118  /* Set the gain mode to automatic */
3119  err = write_reg(dev, GAIN_OVR_EN, 0x00);
3120  if (err < 0)
3121  return err;
3122 
3123  /* Reset the startup sequence */
3124  err = tda1997x_sus_en(dev, 0);
3125  if (err < 0)
3126  return err;
3127 
3128  usleep(1000 * 5);
3129 
3130  err = tda1997x_sus_en(dev, SUS_ENABLE);
3131  if (err < 0)
3132  return err;
3133  } else {
3134  /* Gain mode is already set to automatic. Read gains */
3135  for (i = 0; i < 3; i++) {
3136  err = read_reg(dev, GAIN_CH0 + i, &status);
3137  if (err < 0)
3138  return err;
3139  }
3140  }
3141  }
3142 
3143  /* Detect the resolution */
3144 
3145  /* Set the resolution to detected input */
3146 
3147  /* Colorspace conversion */
3148  err = tda1997x_cfg_conv(dev, (int16_t *) color_conv444);
3149  if (err < 0)
3150  return err;
3151 
3152  /* Set blanking codes */
3153  err = tda1997x_write(dev, BLK_GY_MSB, 6, (uint8_t *) blank_rgb);
3154  if (err < 0)
3155  return err;
3156 
3157  /* The state of the HDMI is now LOCKED */
3158  }
3159 
3160  if (flags & IRQ_SUS_RT_PULSE) {
3161  }
3162 
3163  if (flags & IRQ_SUS_MTP) {
3164  }
3165 
3166  if (flags & IRQ_SUS_FORMAT) {
3167 
3168  /* Ignore format interrupts during MTP process */
3169  if (!(flags & IRQ_SUS_MTP)) {
3170 
3171  err = read_reg(dev, SUS_STATUS, &status);
3172  if (err < 0)
3173  return err;
3174 
3175  if ((status & SUS_STATUS_STATE_MASK) == SUS_STATUS_LAST_STATE)
3176  flags &= ~(IRQ_SUS_FORMAT);
3177 
3178  /* Detect the resolution */
3179 
3180  /* Set the resolution to detected input */
3181 
3182  /* Colorspace conversion */
3183  err = tda1997x_cfg_conv(dev, (int16_t *) color_conv444);
3184  if (err < 0)
3185  return err;
3186 
3187  /* Set blanking codes */
3188  err = tda1997x_write(dev, BLK_GY_MSB, 6, (uint8_t *) blank_rgb);
3189  if (err < 0)
3190  return err;
3191 
3192  /* The state of the HDMI is now LOCKED */
3193  }
3194  }
3195 
3196  return 0;
3197 }
tda1997x_sus_en
static int tda1997x_sus_en(struct tda1997x_dev *dev, uint8_t en)
Enable Startup Sequence.
Definition: tda1997x.c:2056
read_reg
static int read_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t *data)
Read Register.
Definition: tda1997x.c:1836
tda1997x_write
static int tda1997x_write(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t len, uint8_t *data)
Write Data.
Definition: tda1997x.c:1767
tda1997x_cfg_conv
int tda1997x_cfg_conv(struct tda1997x_dev *dev, int16_t *mtx)
Configure Colorspace Conversion.
Definition: tda1997x.c:2083
tda1997x_audio_fifo_rst
static int tda1997x_audio_fifo_rst(struct tda1997x_dev *dev)
Reset Audio FIFO.
Definition: tda1997x.c:2386
write_reg
static int write_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t data)
Write Register.
Definition: tda1997x.c:1849

◆ tda1997x_write()

static int tda1997x_write ( struct tda1997x_dev *  dev,
enum hdmi_reg  reg,
uint8_t  len,
uint8_t *  data 
)
static

#include <projects/lib/tda1997x.c>

Write Data.

Parameters
devTDA1997X device structure pointer
regStart register and page address
lenLength of data to write to device
dataPointer to data to write from
Returns
Number of bytes written or less-than-zero error status
1768 {
1769  int i, err;
1770  struct tda1997x_cfg *cfg = dev->cfg;
1771  uint8_t page = PAGE_OF(reg);
1772 
1773  if (dev->cfg->cur_page != page) {
1774  /* Change the page */
1775  err = cfg->i2c_write(cfg->i2c_addr, (uint8_t)CURPAGE, &page);
1776  if (err < 0) {
1777  printf("[ERROR] %s() %s %d - writing page %02x (%d)\n", __func__, __FILE__, __LINE__, page, err);
1778  return err;
1779  }
1780 
1781  dev->cfg->cur_page = page;
1782  }
1783 
1784  for (i = 0; i < len; i++, data++) {
1785  err = cfg->i2c_write(cfg->i2c_addr, (uint8_t)reg + i, data);
1786  if (err < 0) {
1787  printf("[ERROR] %s() %s %d\n", __func__, __FILE__, __LINE__);
1788  return err;
1789  }
1790  }
1791 
1792  return i;
1793 }
tda1997x_cfg
TDA1997X driver configuration.
Definition: tda1997x.h:138

◆ write_reg()

static int write_reg ( struct tda1997x_dev *  dev,
enum hdmi_reg  reg,
uint8_t  data 
)
static

#include <projects/lib/tda1997x.c>

Write Register.

Parameters
devTDA1997X device structure pointer
regRegister and page address
dataData value to write to register
Returns
Number of bytes written or less-than-zero error status
1850 {
1851  uint8_t tmp = data;
1852 
1853  return tda1997x_write(dev, reg, 1, &tmp);
1854 }
tda1997x_write
static int tda1997x_write(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t len, uint8_t *data)
Write Data.
Definition: tda1997x.c:1767

◆ write_reg_mask()

static int write_reg_mask ( struct tda1997x_dev *  dev,
enum hdmi_reg  reg,
uint8_t  mask,
uint8_t  val 
)
static

#include <projects/lib/tda1997x.c>

Register Mask Write Write a specified value with specified mask bits to a register.

Parameters
devTDA1997X device structure pointer
regRegister and page address
maskMask of bits to be transformed
valBitfield to be written within mask
Returns
Number of bytes written or less-than-zero error status
1867 {
1868  int err;
1869  uint8_t reg_val;
1870 
1871  err = read_reg(dev, reg, &reg_val);
1872  if (err < 0)
1873  return err;
1874 
1875  reg_val &= ~(mask);
1876  reg_val |= val & mask;
1877 
1878  return write_reg(dev, reg, reg_val);
1879 }
read_reg
static int read_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t *data)
Read Register.
Definition: tda1997x.c:1836
write_reg
static int write_reg(struct tda1997x_dev *dev, enum hdmi_reg reg, uint8_t data)
Write Register.
Definition: tda1997x.c:1849

Variable Documentation

◆ blank_rgb

const uint8_t blank_rgb[6]
static

#include <projects/lib/tda1997x.c>

Initial value:
= {
0x00,
0x40,
0x00,
0x40,
0x00,
0x40
}

◆ blank_yuv

const uint8_t blank_yuv[6]
static

#include <projects/lib/tda1997x.c>

Initial value:
= {
0x00,
0x40,
0x02,
0x00,
0x02,
0x00
}

◆ clk_rate

const uint8_t clk_rate[6]
static

#include <projects/lib/tda1997x.c>

Initial value:
= {
0x00,
0x57,
0xE4,
0x03,
0x95,
0xF8
}

◆ color_conv444

const int16_t color_conv444[COLOR_CONV_MATRIX_LENGTH]
static

#include <projects/lib/tda1997x.c>

Initial value:
= {
-256, -2048, -2048,
4096, -2860, -1378,
4096, 5615, 0,
4096, 0, 7097,
256, 256, 256
}

◆ ddc_config

uint8_t ddc_config[8]
static

#include <projects/lib/tda1997x.c>

Initial value:
= {
0x19,
0x41,
0x44,
0x00,
0x04,
0x18,
0x00,
0x00
}

◆ hdcp_seed_tab

const struct tda1997x_mtp_seed hdcp_seed_tab[TDA1997X_SEED_TABLE_LEN]

#include <projects/lib/tda1997x.c>

Initial value:
= {
{ 0xF0, 0x1234 },
{ 0xF1, 0xDBE6 },
{ 0xF2, 0xDBE6 },
{ 0, 0x1234 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ 0, 0 }
}

◆ rgb_full_itu601

const int16_t rgb_full_itu601[COLOR_CONV_MATRIX_LENGTH]
static

#include <projects/lib/tda1997x.c>

Initial value:
= {
0, 0, 0,
2065, 1052, 401,
-1506, 1799, -293,
-1192, -607, 1799,
256, 2048, 2048,
}

◆ rgb_full_itu709

const int16_t rgb_full_itu709[COLOR_CONV_MATRIX_LENGTH]
static

#include <projects/lib/tda1997x.c>

Initial value:
= {
0, 0, 0,
2506, 745, 253,
-1627, 1792, -163,
-1380, -410, 1792,
256, 2048, 2048,
}

◆ rgb_lim_itu601

const int16_t rgb_lim_itu601[COLOR_CONV_MATRIX_LENGTH]
static

#include <projects/lib/tda1997x.c>

Initial value:
= {
-256, -256, -256,
2404, 1225, 467,
-1754, 2095, -341,
-1388, -707, 2095,
256, 2048, 2048,
}

◆ rgb_lim_itu709

const int16_t rgb_lim_itu709[COLOR_CONV_MATRIX_LENGTH]
static

#include <projects/lib/tda1997x.c>

Initial value:
= {
-256, -256, -256,
2918, 867, 295,
-1894, 2087, -190,
-1607, -477, 2087,
256, 2048, 2048,
}

◆ rgb_lim_rgb_full

const int16_t rgb_lim_rgb_full[COLOR_CONV_MATRIX_LENGTH]
static

#include <projects/lib/tda1997x.c>

Initial value:
= {
-256, -256, -256,
4769, 0, 0,
0, 4769, 0,
0
, 0, 4769,
0, 0, 0,
}

◆ rt_config

uint8_t rt_config[6]
static

#include <projects/lib/tda1997x.c>

Initial value:
= {
0x78,
0x03,
0x33,
0xF0,
0x00,
0x00
}

◆ spa_edid

uint16_t spa_edid[2]
static

#include <projects/lib/tda1997x.c>

Initial value:
= {
0x0100,
0x0000,
}

◆ vp_conf444

uint8_t vp_conf444[9]
static

#include <projects/lib/tda1997x.c>

Initial value:
= {
VP_CTRL_A_MSB,
VP_CTRL_A_ISB,
VP_CTRL_HIZ,
VP_CTRL_B_MSB,
VP_CTRL_B_ISB,
VP_CTRL_HIZ,
VP_CTRL_C_MSB,
VP_CTRL_C_ISB,
VP_CTRL_HIZ,
}

◆ vp_conf_mute

uint8_t vp_conf_mute[9]
static

#include <projects/lib/tda1997x.c>

Initial value:
= {
VP_CTRL_HIZ,
VP_CTRL_HIZ,
VP_CTRL_LOZ,
VP_CTRL_HIZ,
VP_CTRL_HIZ,
VP_CTRL_LOZ,
VP_CTRL_HIZ,
VP_CTRL_HIZ,
VP_CTRL_LOZ,
}

◆ yuv601_rgb_full

const int16_t yuv601_rgb_full[COLOR_CONV_MATRIX_LENGTH]
static

#include <projects/lib/tda1997x.c>

Initial value:
= {
-256, -2048, -2048,
4769, -3330, -1602,
4769, 6538, 0,
4769, 0, 8264,
256, 256, 256,
}

◆ yuv709_rgb_full

const int16_t yuv709_rgb_full[COLOR_CONV_MATRIX_LENGTH]
static

#include <projects/lib/tda1997x.c>

Initial value:
= {
-256, -2048, -2048,
4769, -2183, -873,
4769, 7343, 0,
4769, 0, 8652,
0, 0, 0,
}