Global tda1997x_cfg_audio_fmt (struct tda1997x_dev *dev)

Determine the correct register setting for FIFO_LATENCY_CTRL that will eliminate glitches and interruptions in audio stream

Global tda1997x_init (struct tda1997x_dev *dev, struct tda1997x_cfg *cfg, uint8_t *edid_block, uint8_t *edid_ext)

HDCP configuration and activation

Configure video output with structure data

Pass audio configuration data to tda1997x_cfg_audio_fmt

Global tda998x_aud_reset_cts (struct tda998x_dev *dev)

Finish register mask write sequence to reset CTS

Define reset register table

Global tda998x_aud_set_cts (struct tda998x_dev *dev, enum tda998x_cts_ref cts_ref, enum tda998x_aud_rate afs, enum tda998x_vid_fmt vout_fmt, enum tda998x_vert_freq vout_freq, uint32_t cts, uint16_t ctsX, enum tda998x_ctsk ctsK, enum tda998x_ctsm ctsM, enum tda998x_dst_rate dst_rate)

Define CTS values

Reset and release the CTS generator

Global tda998x_aud_set_input (struct tda998x_dev *dev, struct tda998x_audin_cfg *audin_cfg)

Rework the audio configuration

Global tda998x_set_input_output (struct tda998x_dev *dev, struct tda998x_vidin_cfg *vidin_cfg, struct tda998x_vidout_cfg *vidout_cfg, struct tda998x_audin_cfg *audin_cfg, enum tda998x_sink sink)

BEGIN VIDO INPUT SYNCHRONIZATION