piSmasher Configuration Libraries
piSmasher peripheral device configuration libraries
Data Structures | Macros | Enumerations | Functions | Variables
tda998x.c File Reference

TDA998x HDMI Transmitter FreeBSD. More...

#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include <unistd.h>
#include <string.h>
#include <sys/time.h>
#include "tda998x.h"

Data Structures

struct  mtx_offset
 
struct  reg_mask_val
 
struct  tda998x_vid_frm
 
struct  vidfmt_desc
 
struct  vidfmt_map
 

Macros

#define DEBUG_PRINT(...)   do {} while (0)
 
#define PAGE_ADDR(__PAGE__, __ADDR__)   (((__PAGE__) << 8) | ((__ADDR__) & 0xFFU))
 
#define PAGE_OF(__REG__)   (((__REG__) >> 8) & 0xFFU)
 
#define ERR_BAD_PARAM   (0x009U)
 
#define ERR_NOT_PERMITTED   (0x00AU)
 
#define ERR_NULL_PARAM   (0x00BU)
 
#define ERR_ILLEGAL_PARAMS   (0x010U)
 
#define ERR_NOT_FOUND   (0x011U)
 
#define ERR_RESOURCE_NOT_AVAILABLE   (0x012U)
 
#define DDC_EDID_ADDRESS   (0xA0U)
 
#define DDC_EDID_ADDRESS_ALT   (0xA2U)
 
#define DDC_SGMT_PTR_ADDRESS   (0x60U)
 
#define EDID_BLK0_EXT_CNT   (0x7E)
 
#define INTERRUPTSTATUS_CEC   (1 << 0)
 
#define INTERRUPTSTATUS_HDMI   (1 << 1)
 
#define RXSHPDINTENA_ENA_RXS_INT   (1 << 0)
 
#define RXSHPDINTENA_ENA_HPD_INT   (1 << 1)
 
#define RXSHPDINT_RXS_INT   (1 << 0)
 
#define RXSHPDINT_HPD_INT   (1 << 1)
 
#define RXSHPDLEV_RXS_LEVEL   (1 << 0)
 
#define RXSHPDLEV_HPD_LEVEL   (1 << 1)
 
#define ENAMODS_ENA_CEC   (1 << 0)
 
#define ENAMODS_ENA_HDMI   (1 << 1)
 
#define ENAMODS_ENA_RXS   (1 << 2)
 
#define ENAMODS_DIS_CCLK   (1 << 5)
 
#define ENAMODS_DIS_FRO   (1 << 6)
 
#define FRO_IM_CLK_CTRL_FRO_DIV   (1 << 0)
 
#define FRO_IM_CLK_CTRL_IMCLK_SEL   (1 << 1)
 
#define FRO_IM_CLK_CTRL_ENA_OTP   (1 << 6)
 
#define FRO_IM_CLK_CTRL_GHOST_DIS   (1 << 7)
 
#define VERSION_NOT_SCALER   (1 << 4)
 
#define VERSION_NOT_HDCP   (1 << 5)
 
#define MAIN_CNTRL0_SR   (1 << 0)
 
#define MAIN_CNTRL0_DECS   (1 << 1)
 
#define MAIN_CNTRL0_DEHS   (1 << 2)
 
#define MAIN_CNTRL0_CECS   (1 << 3)
 
#define MAIN_CNTRL0_CEHS   (1 << 4)
 
#define MAIN_CNTRL0_SCALER   (1 << 7)
 
#define SR_REG_SR_AUDIO   (1 << 0)
 
#define SR_REG_SR_I2C_MS   (1 << 1)
 
#define DDC_DISABLE_DDC_DIS   (1 << 0)
 
#define CCLK_ON_CCLK_DDC_ON   (1 << 0)
 
#define I2C_MASTER_DIS_MM   (1 << 0)
 
#define I2C_MASTER_DIS_FILT   (1 << 1)
 
#define I2C_MASTER_APP_STRT_LAT   (1 << 2)
 
#define INT_FLAGS_0_ENCRYPT   (1 << 0)
 
#define INT_FLAGS_0_HPD   (1 << 1)
 
#define INT_FLAGS_0_T0   (1 << 2)
 
#define INT_FLAGS_0_BCAPS   (1 << 3)
 
#define INT_FLAGS_0_BSTATUS   (1 << 4)
 
#define INT_FLAGS_0_SHA_1   (1 << 5)
 
#define INT_FLAGS_0_PJ   (1 << 6)
 
#define INT_FLAGS_0_R0   (1 << 7)
 
#define INT_FLAGS_1_VS_RPT   (1 << 0)
 
#define INT_FLAGS_1_OTP   (1 << 1)
 
#define INT_FLAGS_1_SC_IN   (1 << 2)
 
#define INT_FLAGS_1_SC_OUT   (1 << 3)
 
#define INT_FLAGS_1_SC_VID   (1 << 4)
 
#define INT_FLAGS_1_SC_DEIL   (1 << 5)
 
#define INT_FLAGS_1_SW_INT   (1 << 6)
 
#define INT_FLAGS_1_HPD_IN   (1 << 7)
 
#define INT_FLAGS_2_RX_SENSE   (1 << 0)
 
#define INT_FLAGS_2_EDID_BLK_RD   (1 << 1)
 
#define INT_FLAGS_3_RXS_FIL   (1 << 0)
 
#define SW_INT_SW_INT   (1 << 0)
 
#define ENA_ACLK_ENA_ACLK   (1 << 0)
 
#define GND_ACLK_GND_ACLK   (1 << 0)
 
#define ENA_VP_0_ENA_VP0   (1 << 0)
 
#define ENA_VP_0_ENA_VP1   (1 << 1)
 
#define ENA_VP_0_ENA_VP2   (1 << 2)
 
#define ENA_VP_0_ENA_VP3   (1 << 3)
 
#define ENA_VP_0_ENA_VP4   (1 << 4)
 
#define ENA_VP_0_ENA_VP5   (1 << 5)
 
#define ENA_VP_0_ENA_VP6   (1 << 6)
 
#define ENA_VP_0_ENA_VP7   (1 << 7)
 
#define ENA_VP_1_ENA_VP8   (1 << 0)
 
#define ENA_VP_1_ENA_VP9   (1 << 1)
 
#define ENA_VP_1_ENA_VP10   (1 << 2)
 
#define ENA_VP_1_ENA_VP11   (1 << 3)
 
#define ENA_VP_1_ENA_VP12   (1 << 4)
 
#define ENA_VP_1_ENA_VP13   (1 << 5)
 
#define ENA_VP_1_ENA_VP14   (1 << 6)
 
#define ENA_VP_1_ENA_VP15   (1 << 7)
 
#define ENA_VP_2_ENA_VP16   (1 << 0)
 
#define ENA_VP_2_ENA_VP17   (1 << 1)
 
#define ENA_VP_2_ENA_VP18   (1 << 2)
 
#define ENA_VP_2_ENA_VP19   (1 << 3)
 
#define ENA_VP_2_ENA_VP20   (1 << 4)
 
#define ENA_VP_2_ENA_VP21   (1 << 5)
 
#define ENA_VP_2_ENA_VP22   (1 << 6)
 
#define ENA_VP_2_ENA_VP23   (1 << 7)
 
#define ENA_AP_ENA_AP0   (1 << 0)
 
#define ENA_AP_ENA_AP1   (1 << 1)
 
#define ENA_AP_ENA_AP2   (1 << 2)
 
#define ENA_AP_ENA_AP3   (1 << 3)
 
#define ENA_AP_ENA_AP4   (1 << 4)
 
#define ENA_AP_ENA_AP5   (1 << 5)
 
#define ENA_AP_ENA_AP6   (1 << 6)
 
#define ENA_AP_ENA_AP7   (1 << 7)
 
#define VIP_CNTRL_LEN   (3)
 
#define VIP_CNTRL_SWAP_L_SHIFT   (0)
 
#define VIP_CNTRL_MIRR_L   (1 << 3)
 
#define VIP_CNTRL_SWAP_H_SHIFT   (4)
 
#define VIP_CNTRL_MIRR_H   (1 << 7)
 
#define VIP_CNTRL_SWAP_MASK   (0x77U)
 
#define VIP_CNTRL_3_X_TGL   (1 << 0)
 
#define VIP_CNTRL_3_H_TGL   (1 << 1)
 
#define VIP_CNTRL_3_V_TGL   (1 << 2)
 
#define VIP_CNTRL_3_EMB   (1 << 3)
 
#define VIP_CNTRL_3_SP_SYNC_MASK   (0x30U)
 
#define VIP_CNTRL_3_DE_INT   (1 << 6)
 
#define VIP_CNTRL_3_EDGE   (1 << 7)
 
#define VIP_CNTRL_4_BLC_MASK   (0x03U)
 
#define VIP_CNTRL_4_BLNKIT_MASK   (0x0CU)
 
#define VIP_CNTRL_4_CCIR656   (1 << 4)
 
#define VIP_CNTRL_4_656_ALT   (1 << 5)
 
#define VIP_CNTRL_4_TST_656   (1 << 6)
 
#define VIP_CNTRL_4_TST_PAT   (1 << 7)
 
#define VIDFORMAT_FMT_MASK   (0x1FU)
 
#define REFPIX_MIN   (0x0000U)
 
#define REFPIX_MAX   (0x1FFFU)
 
#define REFLINE_MIN   (0x0000U)
 
#define REFLINE_MAX   (0x07FFU)
 
#define VIP_CNTRL_5_CLKPOL   (1 << 0)
 
#define VIP_CNTRL_5_SP_CNT_MASK   (0x06U)
 
#define VIP_CNTRL_5_SP_CNT_SHIFT   (1)
 
#define MUX_AP_SELECT_I2S   (0x64)
 
#define MUX_AP_SELECT_SPDIF   (0x24)
 
#define PIXREP_NONE   (0)
 
#define PIXREP_MIN   (0)
 
#define PIXREP_MAX   (9)
 
#define PIXREP_DEFAULT   (10)
 
#define MTX_CNTRL_MTX_SC   (0x03U)
 
#define MTX_CNTRL_MTX_BP   (1 << 2)
 
#define MTX_OFFSET_LEN   (3)
 
#define TBG_CNTRL_0_SYNC   (1 << 7)
 
#define TBG_CNTRL_0_SYNC_MTHD   (1 << 6)
 
#define TBG_CNTRL_0_FRAME_DIS   (1 << 5)
 
#define TBG_CNTRL_1_VH_TGL_MASK   (0x07U)
 
#define TBG_CNTRL_1_VH_TGL_0   (1 << 0)
 
#define TBG_CNTRL_1_VH_TGL_1   (1 << 1)
 
#define TBG_CNTRL_1_VH_TGL_2   (1 << 2)
 
#define TBG_CNTRL_1_VHX_EXT_MASK   (0x38U)
 
#define TBG_CNTRL_1_VHX_EXT_DE   (1 << 3)
 
#define TBG_CNTRL_1_VHX_EXT_HS   (1 << 4)
 
#define TBG_CNTRL_1_VHX_EXT_VS   (1 << 5)
 
#define TBG_CNTRL_1_DWIN_DIS   (1 << 6)
 
#define I2C_TIMER_RI_MASK   (0x0FU)
 
#define I2C_TIMER_PJ_MASK   (0xF0U)
 
#define HVF_CNTRL_0_INTPOL_MASK   (0x03U)
 
#define HVF_CNTRL_0_PREFIL_MASK   (0x0CU)
 
#define HVF_CNTRL_0_CLRBAR   (1 << 6)
 
#define HVF_CNTRL_0_SM   (1 << 7)
 
#define HVF_CNTRL_1_FOR   (1 << 0)
 
#define HVF_CNTRL_1_YUVBLK   (1 << 1)
 
#define HVF_CNTRL_1_VQR_MASK   (0x0CU)
 
#define HVF_CNTRL_1_PAD_MASK   (0x30U)
 
#define HVF_CNTRL_1_SEMI_PLANAR   (1 << 6)
 
#define TIMER_H_TIM_H_MASK   (0x03U)
 
#define TIMER_H_WD_CLKSEL   (1 << 6)
 
#define DEBUG_PROBE_WOO_EN   (1 << 0)
 
#define DEBUG_PROBE_DI_DE   (1 << 1)
 
#define DEBUG_PROBE_VID_DE   (1 << 2)
 
#define DEBUG_PROBE_BYPASS   (1 << 3)
 
#define DEBUG_PROBE_SEL_MASK   (0x30U)
 
#define I2S_FORMAT_I2S_FORMAT_MASK   (0x0FU)
 
#define I2S_FORMAT_I2S_DATA_SIZE_MASK   (0x0CU)
 
#define AIP_CLKSEL_DST_RATE   (1 << 6)
 
#define AIP_CLKSEL_SEL_AIP_MASK   (0x38U)
 
#define AIP_CLKSEL_SEL_POL_CLK   (1 << 2)
 
#define AIP_CLKSEL_SEL_FS_MASK   (0x03U)
 
#define SC_VIDFORMAT_LUT_SEL_MASK   (0xC0U)
 
#define SC_VIDFORMAT_VID_FORMAT_O_MASK   (0x38U)
 
#define SC_VIDFORMAT_VID_FORMAT_I_MASK   (0x0FU)
 
#define SC_CNTRL_PHASES_H   (1 << 4)
 
#define SC_CNTRL_IL_OUT_ON   (1 << 3)
 
#define SC_CNTRL_PHASES_V   (1 << 2)
 
#define SC_CNTRL_VS_ON   (1 << 1)
 
#define SC_CNTRL_DEIL_ON   (1 << 0)
 
#define TBG_CNTRL_0_SYNC   (1 << 7)
 
#define TBG_CNTRL_0_SYNC_MTHD   (1 << 6)
 
#define TBG_CNTRL_0_FRAME_DIS   (1 << 5)
 
#define TBG_CNTRL_0_TOP_EXT   (1 << 3)
 
#define TBG_CNTRL_0_DE_EXT   (1 << 2)
 
#define TBG_CNTRL_0_TOP_SEL   (1 << 1)
 
#define TBG_CNTRL_0_TOP_TGL   (1 << 0)
 
#define PLL_SERIAL_1_SRL_FDN   (1 << 0)
 
#define PLL_SERIAL_1_SRL_IZ_MASK   (0x06U)
 
#define PLL_SERIAL_1_SRL_MAN_IZ   (1 << 6)
 
#define PLL_SERIAL_2_SRL_NOSC_MASK   (0x03U)
 
#define PLL_SERIAL_2_SRL_PR_MASK   (0xF0U)
 
#define PLL_SERIAL_3_SRL_CCIR   (1 << 0)
 
#define PLL_SERIAL_3_SRL_DE   (1 << 1)
 
#define PLL_SERIAL_3_SRL_PXIN_SEL   (1 << 4)
 
#define SERIALIZER_SRL_PHASE2_MASK   (0x0FU)
 
#define SERIALIZER_SRL_PHASE3_MASK   (0xF0U)
 
#define BUFFER_OUT_SRL_CLK_MASK   (0x03U)
 
#define BUFFER_OUT_SRL_FORCE_MASK   (0x0CU)
 
#define PLL_SCG1_SCG_FDN   (1 << 0)
 
#define PLL_SCG2_SCG_NOSC_MASK   (0x03U)
 
#define PLL_SCG2_SELPLLCLKIN   (1 << 4)
 
#define PLL_SCG2_BYPASS_SCG   (1 << 7)
 
#define VAI_PLL_PLLSRL_LOCK   (1 << 0)
 
#define VAI_PLL_PLLSCG_LOCK   (1 << 1)
 
#define VAI_PLL_PLLSRL_HVP   (1 << 4)
 
#define VAI_PLL_PLLSCG_HVP   (1 << 5)
 
#define VAI_PLL_PLLDE_HVP   (1 << 6)
 
#define AUDIO_DIV_AUDIO_DIV_MASK   (0x07U)
 
#define AIP_CNTRL_0_RST_FIFO   (1 << 0)
 
#define AIP_CNTRL_0_SWAP   (1 << 1)
 
#define AIP_CNTRL_0_LAYOUT   (1 << 2)
 
#define AIP_CNTRL_0_ACR_MAN   (1 << 5)
 
#define AIP_CNTRL_0_RST_CTS   (1 << 6)
 
#define TEST1_TST_ENAHVP   (1 << 0)
 
#define TEST1_TST_NOSC   (1 << 1)
 
#define TEST1_SRLDAT_MASK   (0xC0U)
 
#define TEST2_DIVTESTOE   (1 << 0)
 
#define TEST2_PWD1V8   (1 << 1)
 
#define SEL_CLK_SEL_CLK1   (1 << 0)
 
#define SEL_CLK_SEL_VRF_CLK_MASK   (0x06U)
 
#define SEL_CLK_ENA_SC_CLK   (1 << 3)
 
#define BUFF_OUT2_FORCE_DAT0_MASK   (0x03U)
 
#define BUFF_OUT2_FORCE_DAT1_MASK   (0x0CU)
 
#define BUFF_OUT2_FORCE_DAT2_MASK   (0x30U)
 
#define EDID_CTRL_EDID_RD   (1 << 0)
 
#define CA_I2S_CA_I2S_MASK   (0x1FU)
 
#define CA_I2S_HBR_CHSTAT_4   (1 << 5)
 
#define GC_AVMUTE_SETCLR_MUTE   (0x0CU)
 
#define GC_AVMUTE_CLR_MUTE   (1 << 0)
 
#define GC_AVMUTE_SET_MUTE   (1 << 1)
 
#define CTS_N_M_SEL_MASK   (0x30U)
 
#define CTS_N_K_SEL_MASK   (0x07U)
 
#define ENC_CNTRL_RST_ENC   (1 << 0)
 
#define ENC_CNTRL_RST_SEL   (1 << 1)
 
#define ENC_CNTRL_CTL_CODE_MASK   (0x0CU)
 
#define DIP_FLAGS_ACR   (1 << 0)
 
#define DIP_FLAGS_GC   (1 << 1)
 
#define DIP_FLAGS_ISRC1   (1 << 2)
 
#define DIP_FLAGS_ISRC2   (1 << 3)
 
#define DIP_FLAGS_ACP   (1 << 4)
 
#define DIP_FLAGS_NULL   (1 << 6)
 
#define DIP_FLAGS_FORCE_NULL   (1 << 7)
 
#define DIP_IF_FLAGS_IF1   (1 << 1)
 
#define DIP_IF_FLAGS_IF2   (1 << 2)
 
#define DIP_IF_FLAGS_IF3   (1 << 3)
 
#define DIP_IF_FLAGS_IF4   (1 << 4)
 
#define DIP_IF_FLAGS_IF5   (1 << 5)
 
#define OTP_TX0_SR_HDCP   (1 << 0)
 
#define DDC_SPEED_FACTOR   (39)
 
#define OTP_TX33_HDMI   (1 << 1)
 
#define GMD_CONTROL_ENABLE   (1 << 0)
 
#define GMD_CONTROL_BUF_SEL   (1 << 1)
 
#define SSD_UNUSED_VALUE   0xF0
 
#define REG_VAL_SEL_AIP_SPDIF   0
 
#define REG_VAL_SEL_AIP_I2S   1
 
#define REG_VAL_SEL_AIP_OBA   2
 
#define REG_VAL_SEL_AIP_DST   3
 
#define REG_VAL_SEL_AIP_HBR   5
 
#define CH_STAT_B_0_DATA_PCM   (1 << 1)
 
#define CH_STAT_B_0_COPYRIGHT   (1 << 2)
 
#define CH_STAT_B_0_FMT_MASK   (0x38U)
 

Enumerations

enum  tda998x_cec_reg {
  INTERRUPTSTATUS = 0xEE, RXSHPDINTENA = 0xFC, RXSHPDINT = 0xFD, RXSHPDLEV = 0xFE,
  ENAMODS = 0xFF, FRO_IM_CLK_CTRL = 0xFB
}
 CEC Core Registers.
 
enum  tda998x_hdmi_page {
  PAGE_00 = 0x00, PAGE_01 = 0x01, PAGE_02 = 0x02, PAGE_09 = 0x09,
  PAGE_10 = 0x10, PAGE_11 = 0x11, PAGE_12 = 0x12, PAGE_13 = 0x13,
  PAGE_INVALID = 0xFF
}
 HDMI Core Register Pages.
 
enum  vip_cntrl_swap {
  VIP_CNTRL_VP23_20 = 0x00, VIP_CNTRL_VP19_16 = 0x01, VIP_CNTRL_VP15_12 = 0x02, VIP_CNTRL_VP11_8 = 0x03,
  VIP_CNTRL_VP7_4 = 0x04, VIP_CNTRL_VP3_0 = 0x05
}
 
enum  vip_cntrl_mirr { VIP_CNTRL_NOT_MIRRORED = 0, VIP_CNTRL_MIRRORED = 1 }
 
enum  vip_cntrl_3_emb { EMB_DISABLE = 0, EMB_ENABLE = VIP_CNTRL_3_EMB }
 
enum  vip_cntrl_3_sp_sync { SPSYNC_HEMB = 0, SPSYNC_RISING_DE = 0x10, SPSYNC_RISING_HS = 0x20, SPSYNC_FIXED = 0x30 }
 Video Input Port Control Subpacket Synchronization Enumeration.
 
enum  vip_cntrl_3_edge { PIXEDGE_POS = 0, PIXEDGE_NEG = VIP_CNTRL_3_EDGE }
 
enum  vip_cntrl_4_blc { BLNKCODE_ALL_0 = 0x00, BLNKCODE_RGB444 = 0x01, BLNKCODE_YUV444 = 0x02, BLNKCODE_YUV422 = 0x03 }
 Video Input Port Control Blanking Code Enumeration. More...
 
enum  vip_cntrl_4_blnkit { BLNKSRC_NOT_DE = 0x00, BLNKSRC_VS_HS = 0x04, BLNKSRC_VS_NOT_HS = 0x08, BLNKSRC_VS_HEMB_VEMB = 0x0C }
 Video Input Port Control Blanking Source Enumeration. More...
 
enum  vidformat_fmt {
  VIDFORMAT_640x480p_60Hz = 0x00, VIDFORMAT_720x480p_60Hz = 0x01, VIDFORMAT_1280x720p_60Hz = 0x02, VIDFORMAT_1920x1080i_60Hz = 0x03,
  VIDFORMAT_720x480i_60Hz = 0x04, VIDFORMAT_720x240p_60Hz = 0x05, VIDFORMAT_1920x1080p_60Hz = 0x06, VIDFORMAT_720x576p_50Hz = 0x07,
  VIDFORMAT_1280x720p_50Hz = 0x08, VIDFORMAT_1920x1080i_50Hz = 0x09, VIDFORMAT_720x576i_50Hz = 0x0A, VIDFORMAT_720x288p_50Hz = 0x0B,
  VIDFORMAT_1920x1080p_50Hz = 0x0C, VIDFORMAT_800x600p_60Hz, VIDFORMAT_1024x768p_60Hz, VIDFORMAT_1280x768p_60Hz,
  VIDFORMAT_1366x768p_60Hz, VIDFORMAT_1600x1200p_60Hz, VIDFORMAT_1920x1200p_60Hz
}
 Video Format Enumeration.
 
enum  vip_cntrl_5_clkpol { TGLCLK_LOW = 0, TGLCLK_HIGH = VIP_CNTRL_5_CLKPOL }
 Video Input Port Control Clock Polarity Enumeration. More...
 
enum  mtx_cntrl_scale { MTXSCALE_256 = 0, MTXSCALE_512 = 1, MTXSCALE_1024 = 2 }
 Matrix Control Scale Enumeration. More...
 
enum  mtx_cntrl_bp { MTXBYPASS_OFF = 0, MTXBYPASS_ON = MTX_CNTRL_MTX_BP }
 Matrix Control Bypass Enumeration. More...
 
enum  hvf_cntrl_0_prefil { PREFIL_OFF = 0, PREFIL_121 = 0x04, PREFIL_109 = 0x08, PREFIL_CCIR601 = 0x0C }
 HDMI Video Formatter Control Prefilter Enumeration.
 
enum  hvf_cntrl_0_clrbar { CLRBAR_4BAR = 0, CLRBAR_8BAR = HVF_CNTRL_0_CLRBAR }
 
enum  hvf_cntrl_1_yuv_blk { YUVBLK_16 = 0, YUVBLK_0 = HVF_CNTRL_1_YUVBLK }
 HDMI Video Formatter Control Blanking Level Enumeration. More...
 
enum  hvf_cntrl_1_vqr { QRANGE_FS = 0, QRANGE_RGB_YUV = 0x04, QRANGE_YUV = 0x08 }
 HDMI Video Formatter Control Video Quantization Range Enumeration. More...
 
enum  hvf_cntrl_1_pad { DATAPATH_BITS_12 = 0, DATAPATH_BITS_10 = 0x10, DATAPATH_BITS_8 = 0x20 }
 HDMI Video Formatter Control Datapath. More...
 
enum  tbg_cntrl_0_sync { SYNC_EACH_FRAME = 0, SYNC_ONCE = TBG_CNTRL_0_SYNC }
 
enum  tbg_cntrl_0_sync_mthd { SYNCMTHD_V_H = 0, SYNCMTHD_V_XDE = TBG_CNTRL_0_SYNC_MTHD }
 
enum  buffer_out_srl_force { TMDSOUT_NORMAL = 0x00, TMDSOUT_NORMAL1 = 0x04, TMDSOUT_FORCED0 = 0x08, TMDSOUT_FORCED1 = 0x0C }
 Buffer Output Serializer Force Enumeration.
 
enum  tda998x_hdmi_reg {
  VERSION = PAGE_ADDR(PAGE_00, 0x00), MAIN_CNTRL0 = PAGE_ADDR(PAGE_00, 0x01), VERSION_MSB = PAGE_ADDR(PAGE_00, 0x02), PACKAGE_TYPE = PAGE_ADDR(PAGE_00, 0x03),
  SR_REG = PAGE_ADDR(PAGE_00, 0x0A), DDC_DISABLE = PAGE_ADDR(PAGE_00, 0x0B), CCLK_ON = PAGE_ADDR(PAGE_00, 0x0C), I2C_MASTER = PAGE_ADDR(PAGE_00, 0x0D),
  INT_FLAGS_0 = PAGE_ADDR(PAGE_00, 0x0F), INT_FLAGS_1 = PAGE_ADDR(PAGE_00, 0x10), INT_FLAGS_2 = PAGE_ADDR(PAGE_00, 0x11), INT_FLAGS_3 = PAGE_ADDR(PAGE_00, 0x12),
  SW_INT = PAGE_ADDR(PAGE_00, 0x15), ENA_ACLK = PAGE_ADDR(PAGE_00, 0x16), ENA_VP_0 = PAGE_ADDR(PAGE_00, 0x18), ENA_VP_1 = PAGE_ADDR(PAGE_00, 0x19),
  ENA_VP_2 = PAGE_ADDR(PAGE_00, 0x1A), ENA_AP = PAGE_ADDR(PAGE_00, 0x1E), VIP_CNTRL_0 = PAGE_ADDR(PAGE_00, 0x20), VIP_CNTRL_1 = PAGE_ADDR(PAGE_00, 0x21),
  VIP_CNTRL_2 = PAGE_ADDR(PAGE_00, 0x22), VIP_CNTRL_3 = PAGE_ADDR(PAGE_00, 0x23), VIP_CNTRL_4 = PAGE_ADDR(PAGE_00, 0x24), VIP_CNTRL_5 = PAGE_ADDR(PAGE_00, 0x25),
  MUX_AP = PAGE_ADDR(PAGE_00, 0x26), MUX_VP_VIP_OUT = PAGE_ADDR(PAGE_00, 0x27), MTX_CNTRL = PAGE_ADDR(PAGE_00, 0x80), MTX_OI1_MSB = PAGE_ADDR(PAGE_00, 0x81),
  MTX_P11_MSB = PAGE_ADDR(PAGE_00, 0x87), MTX_OO1_MSB = PAGE_ADDR(PAGE_00, 0x99), VIDFORMAT = PAGE_ADDR(PAGE_00, 0xA0), REFPIX_MSB = PAGE_ADDR(PAGE_00, 0xA1),
  REFPIX_LSB = PAGE_ADDR(PAGE_00, 0xA2), REFLINE_MSB = PAGE_ADDR(PAGE_00, 0xA3), REFLINE_LSB = PAGE_ADDR(PAGE_00, 0xA4), NPIX_MSB = PAGE_ADDR(PAGE_00, 0xA5),
  NPIX_LSB = PAGE_ADDR(PAGE_00, 0xA6), NLINE_MSB = PAGE_ADDR(PAGE_00, 0xA7), NLINE_LSB = PAGE_ADDR(PAGE_00, 0xA8), VS_LINE_STRT_1_MSB = PAGE_ADDR(PAGE_00, 0xA9),
  VS_LINE_STRT_1_LSB = PAGE_ADDR(PAGE_00, 0xAA), VS_PIX_STRT_1_MSB = PAGE_ADDR(PAGE_00, 0xAB), VS_PIX_STRT_1_LSB = PAGE_ADDR(PAGE_00, 0xAC), VS_LINE_END_1_MSB = PAGE_ADDR(PAGE_00, 0xAD),
  VS_LINE_END_1_LSB = PAGE_ADDR(PAGE_00, 0xAE), VS_PIX_END_1_MSB = PAGE_ADDR(PAGE_00, 0xAF), VS_PIX_END_1_LSB = PAGE_ADDR(PAGE_00, 0xB0), VS_LINE_STRT_2_MSB = PAGE_ADDR(PAGE_00, 0xB1),
  VS_LINE_STRT_2_LSB = PAGE_ADDR(PAGE_00, 0xB2), VS_PIX_STRT_2_MSB = PAGE_ADDR(PAGE_00, 0xB3), VS_PIX_STRT_2_LSB = PAGE_ADDR(PAGE_00, 0xB4), VS_LINE_END_2_MSB = PAGE_ADDR(PAGE_00, 0xB5),
  VS_LINE_END_2_LSB = PAGE_ADDR(PAGE_00, 0xB6), VS_PIX_END_2_MSB = PAGE_ADDR(PAGE_00, 0xB7), VS_PIX_END_2_LSB = PAGE_ADDR(PAGE_00, 0xB8), HS_PIX_START_MSB = PAGE_ADDR(PAGE_00, 0xB9),
  HS_PIX_START_LSB = PAGE_ADDR(PAGE_00, 0xBA), HS_PIX_STOP_MSB = PAGE_ADDR(PAGE_00, 0xBB), HS_PIX_STOP_LSB = PAGE_ADDR(PAGE_00, 0xBC), VWIN_START_1_MSB = PAGE_ADDR(PAGE_00, 0xBD),
  VWIN_START_1_LSB = PAGE_ADDR(PAGE_00, 0xBE), VWIN_END_1_MSB = PAGE_ADDR(PAGE_00, 0xBF), VWIN_END_1_LSB = PAGE_ADDR(PAGE_00, 0xC0), VWIN_START_2_MSB = PAGE_ADDR(PAGE_00, 0xC1),
  VWIN_START_2_LSB = PAGE_ADDR(PAGE_00, 0xC2), VWIN_END_2_MSB = PAGE_ADDR(PAGE_00, 0xC3), VWIN_END_2_LSB = PAGE_ADDR(PAGE_00, 0xC4), DE_START_MSB = PAGE_ADDR(PAGE_00, 0xC5),
  DE_START_LSB = PAGE_ADDR(PAGE_00, 0xC6), DE_STOP_MSB = PAGE_ADDR(PAGE_00, 0xC7), DE_STOP_LSB = PAGE_ADDR(PAGE_00, 0xC8), COLBAR_WIDTH = PAGE_ADDR(PAGE_00, 0xC9),
  TBG_CNTRL_0 = PAGE_ADDR(PAGE_00, 0xCA), TBG_CNTRL_1 = PAGE_ADDR(PAGE_00, 0xCB), VBL_OFFSET_START = PAGE_ADDR(PAGE_00, 0xCC), VBL_OFFSET_END = PAGE_ADDR(PAGE_00, 0xCD),
  HBL_OFFSET_START = PAGE_ADDR(PAGE_00, 0xCE), HBL_OFFSET_END = PAGE_ADDR(PAGE_00, 0xCF), DWIN_RE_DE = PAGE_ADDR(PAGE_00, 0xD0), DWIN_FE_DE = PAGE_ADDR(PAGE_00, 0xD1),
  TIMER_RI_PJ = PAGE_ADDR(PAGE_00, 0xE1), BCAPS_POLL = PAGE_ADDR(PAGE_00, 0xE2), REG_100us = PAGE_ADDR(PAGE_00, 0xE3), HVF_CNTRL_0 = PAGE_ADDR(PAGE_00, 0xE4),
  HVF_CNTRL_1 = PAGE_ADDR(PAGE_00, 0xE5), TIMER_H = PAGE_ADDR(PAGE_00, 0xE8), TIMER_M = PAGE_ADDR(PAGE_00, 0xE9), TIMER_L = PAGE_ADDR(PAGE_00, 0xEA),
  TIMER_2SEC = PAGE_ADDR(PAGE_00, 0xEB), TIMER_5SEC = PAGE_ADDR(PAGE_00, 0xEC), NDIV_IM = PAGE_ADDR(PAGE_00, 0xEE), NDIV_PF = PAGE_ADDR(PAGE_00, 0xEF),
  RPT_CNTRL = PAGE_ADDR(PAGE_00, 0xF0), LEAD_OFF = PAGE_ADDR(PAGE_00, 0xF1), TRAIL_OFF = PAGE_ADDR(PAGE_00, 0xF2), MISR_EXP_0 = PAGE_ADDR(PAGE_00, 0xF3),
  MISR_EXP_1 = PAGE_ADDR(PAGE_00, 0xF4), MISR_EXP_2 = PAGE_ADDR(PAGE_00, 0xF5), MISR_0 = PAGE_ADDR(PAGE_00, 0xF6), MISR_1 = PAGE_ADDR(PAGE_00, 0xF7),
  DEBUG_PROBE = PAGE_ADDR(PAGE_00, 0xF8), GHOST_XADDR = PAGE_ADDR(PAGE_00, 0xF9), MISR_2 = PAGE_ADDR(PAGE_00, 0xFA), I2S_FORMAT = PAGE_ADDR(PAGE_00, 0xFC),
  AIP_CLKSEL = PAGE_ADDR(PAGE_00, 0xFD), GHOST_ADDR = PAGE_ADDR(PAGE_00, 0xFE), SC_VIDFORMAT = PAGE_ADDR(PAGE_01, 0x00), SC_CNTRL = PAGE_ADDR(PAGE_01, 0x01),
  SC_DELTA_PHASE_V = PAGE_ADDR(PAGE_01, 0x02), SC_DELTA_PHASE_H = PAGE_ADDR(PAGE_01, 0x03), SC_START_PHASE_H = PAGE_ADDR(PAGE_01, 0x04), SC_NPIX_IN_LSB = PAGE_ADDR(PAGE_01, 0x05),
  SC_NPIX_IN_MSB = PAGE_ADDR(PAGE_01, 0x06), SC_NPIX_OUT_LSB = PAGE_ADDR(PAGE_01, 0x07), SC_NPIX_OUT_MSB = PAGE_ADDR(PAGE_01, 0x08), SC_NLINE_IN_LSB = PAGE_ADDR(PAGE_01, 0x09),
  SC_NLINE_IN_MSB = PAGE_ADDR(PAGE_01, 0x0A), SC_NLINE_OUT_LSB = PAGE_ADDR(PAGE_01, 0x0B), SC_NLINE_OUT_MSB = PAGE_ADDR(PAGE_01, 0x0C), SC_NLINE_SKIP = PAGE_ADDR(PAGE_01, 0x0D),
  SC_SAMPLE_BUFFIL = PAGE_ADDR(PAGE_01, 0x0E), SC_MAX_BUFFILL_P_0 = PAGE_ADDR(PAGE_01, 0x0F), SC_MAX_BUFFILL_P_1 = PAGE_ADDR(PAGE_01, 0x10), SC_MAX_BUFFILL_D_0 = PAGE_ADDR(PAGE_01, 0x11),
  SC_MAX_BUFFILL_D_1 = PAGE_ADDR(PAGE_01, 0x12), SC_SAMPLE_FIFOFILL = PAGE_ADDR(PAGE_01, 0x13), SC_MAX_FIFOFILL_PI = PAGE_ADDR(PAGE_01, 0x14), SC_MIN_FIFOFILL_PO1 = PAGE_ADDR(PAGE_01, 0x15),
  SC_MIN_FIFOFILL_PO2 = PAGE_ADDR(PAGE_01, 0x16), SC_MIN_FIFOFILL_PO3 = PAGE_ADDR(PAGE_01, 0x17), SC_MIN_FIFOFILL_PO4 = PAGE_ADDR(PAGE_01, 0x18), SC_MAX_FIFOFILL_DI = PAGE_ADDR(PAGE_01, 0x19),
  SC_MAX_FIFOFILL_DO = PAGE_ADDR(PAGE_01, 0x1A), SC_VS_LUT_0 = PAGE_ADDR(PAGE_01, 0x1B), SC_LAT_SCO = PAGE_ADDR(PAGE_01, 0x48), VIDFORMAT_W = PAGE_ADDR(PAGE_01, 0xA0),
  REFPIX_MSB_W = PAGE_ADDR(PAGE_01, 0xA1), REFPIX_LSB_W = PAGE_ADDR(PAGE_01, 0xA2), REFLINE_MSB_W = PAGE_ADDR(PAGE_01, 0xA3), REFLINE_LSB_W = PAGE_ADDR(PAGE_01, 0xA4),
  NPIX_MSB_W = PAGE_ADDR(PAGE_01, 0xA5), NPIX_LSB_W = PAGE_ADDR(PAGE_01, 0xA6), NLINE_MSB_W = PAGE_ADDR(PAGE_01, 0xA7), NLINE_LSB_W = PAGE_ADDR(PAGE_01, 0xA8),
  VWIN_START_1_MSB_W = PAGE_ADDR(PAGE_01, 0xBD), VWIN_START_1_LSB_W = PAGE_ADDR(PAGE_01, 0xBE), VWIN_END_1_MSB_W = PAGE_ADDR(PAGE_01, 0xBF), VWIN_END_1_LSB_W = PAGE_ADDR(PAGE_01, 0xC0),
  VWIN_START_2_MSB_W = PAGE_ADDR(PAGE_01, 0xC1), VWIN_START_2_LSB_W = PAGE_ADDR(PAGE_01, 0xC2), VWIN_END_2_MSB_W = PAGE_ADDR(PAGE_01, 0xC3), VWIN_END_2_LSB_W = PAGE_ADDR(PAGE_01, 0xC4),
  DE_START_MSB_W = PAGE_ADDR(PAGE_01, 0xC5), DE_START_LSB_W = PAGE_ADDR(PAGE_01, 0xC6), DE_STOP_MSB_W = PAGE_ADDR(PAGE_01, 0xC7), DE_STOP_LSB_W = PAGE_ADDR(PAGE_01, 0xC8),
  PLL_SERIAL_1 = PAGE_ADDR(PAGE_02, 0x00), PLL_SERIAL_2 = PAGE_ADDR(PAGE_02, 0x01), PLL_SERIAL_3 = PAGE_ADDR(PAGE_02, 0x02), SERIALIZER = PAGE_ADDR(PAGE_02, 0x03),
  BUFFER_OUT = PAGE_ADDR(PAGE_02, 0x04), PLL_SCG1 = PAGE_ADDR(PAGE_02, 0x05), PLL_SCG2 = PAGE_ADDR(PAGE_02, 0x06), PLL_SCGN1 = PAGE_ADDR(PAGE_02, 0x07),
  PLL_SCGN2 = PAGE_ADDR(PAGE_02, 0x08), PLL_SCGR1 = PAGE_ADDR(PAGE_02, 0x09), PLL_SCGR2 = PAGE_ADDR(PAGE_02, 0x0A), VAI_PLL_R = PAGE_ADDR(PAGE_02, 0x0D),
  AUDIO_DIV = PAGE_ADDR(PAGE_02, 0x0E), TEST1_RW = PAGE_ADDR(PAGE_02, 0x0F), TEST2_RW = PAGE_ADDR(PAGE_02, 0x10), SEL_CLK = PAGE_ADDR(PAGE_02, 0x11),
  ANA_GENERAL = PAGE_ADDR(PAGE_02, 0x12), BUFFER_OUT2_RW = PAGE_ADDR(PAGE_02, 0x13), SRL_TSTPAT0_RW = PAGE_ADDR(PAGE_02, 0x14), SRL_TSTPAT1_RW = PAGE_ADDR(PAGE_02, 0x15),
  SRL_TSTPAT2_RW = PAGE_ADDR(PAGE_02, 0x16), SRL_TSTPAT3_RW = PAGE_ADDR(PAGE_02, 0x17), EDID_DATA_0_R = PAGE_ADDR(PAGE_09, 0x00), EDID_CTRL_RW = PAGE_ADDR(PAGE_09, 0xFA),
  DDC_ADDR_RW = PAGE_ADDR(PAGE_09, 0xFB), DDC_OFFS_RW = PAGE_ADDR(PAGE_09, 0xFC), DDC_SEGM_ADDR_RW = PAGE_ADDR(PAGE_09, 0xFD), DDC_SEGM_RW = PAGE_ADDR(PAGE_09, 0xFE),
  IF1_HB0 = PAGE_ADDR(PAGE_10, 0x20), IF1_PB0 = PAGE_ADDR(PAGE_10, 0x23), IF1_PB10 = PAGE_ADDR(PAGE_10, 0x2D), IF2_HB0 = PAGE_ADDR(PAGE_10, 0x40),
  IF2_PB0 = PAGE_ADDR(PAGE_10, 0x43), IF3_HB0 = PAGE_ADDR(PAGE_10, 0x60), IF3_PB0 = PAGE_ADDR(PAGE_10, 0x63), IF4_HB0 = PAGE_ADDR(PAGE_10, 0x80),
  IF4_PB0 = PAGE_ADDR(PAGE_10, 0x83), IF5_HB0 = PAGE_ADDR(PAGE_10, 0xA0), IF5_PB0 = PAGE_ADDR(PAGE_10, 0xA3), AIP_CNTRL_0 = PAGE_ADDR(PAGE_11, 0x00),
  CA_I2S = PAGE_ADDR(PAGE_11, 0x01), CA_DSD = PAGE_ADDR(PAGE_11, 0x02), OBA_PH = PAGE_ADDR(PAGE_11, 0x03), LATENCY_RD = PAGE_ADDR(PAGE_11, 0x04),
  ACR_CTS_0 = PAGE_ADDR(PAGE_11, 0x05), ACR_CTS_1 = PAGE_ADDR(PAGE_11, 0x06), ACR_CTS_2 = PAGE_ADDR(PAGE_11, 0x07), ACR_N_0 = PAGE_ADDR(PAGE_11, 0x08),
  ACR_N_1 = PAGE_ADDR(PAGE_11, 0x09), ACR_N_2 = PAGE_ADDR(PAGE_11, 0x0A), GC_AVMUTE = PAGE_ADDR(PAGE_11, 0x0B), CTS_N_RW = PAGE_ADDR(PAGE_11, 0x0C),
  ENC_CNTRL = PAGE_ADDR(PAGE_11, 0x0D), DIP_FLAGS = PAGE_ADDR(PAGE_11, 0x0E), DIP_IF_FLAGS = PAGE_ADDR(PAGE_11, 0x0F), CH_STAT_B_0 = PAGE_ADDR(PAGE_11, 0x14),
  CH_STAT_B_1 = PAGE_ADDR(PAGE_11, 0x15), CH_STAT_B_3 = PAGE_ADDR(PAGE_11, 0x16), CH_STAT_B_4 = PAGE_ADDR(PAGE_11, 0x17), CH_STAT_B_2_AP0_L = PAGE_ADDR(PAGE_11, 0x18),
  CH_STAT_B_2_AP0_R = PAGE_ADDR(PAGE_11, 0x19), CH_STAT_B_2_AP1_L = PAGE_ADDR(PAGE_11, 0x1A), CH_STAT_B_2_AP1_R = PAGE_ADDR(PAGE_11, 0x1B), CH_STAT_B_2_AP2_L = PAGE_ADDR(PAGE_11, 0x1C),
  CH_STAT_B_2_AP2_R = PAGE_ADDR(PAGE_11, 0x1D), CH_STAT_B_2_AP3_L = PAGE_ADDR(PAGE_11, 0x1E), CH_STAT_B_2_AP3_R = PAGE_ADDR(PAGE_11, 0x1F), ISRC1_HB0 = PAGE_ADDR(PAGE_11, 0x20),
  ISRC1_PB0 = PAGE_ADDR(PAGE_11, 0x23), ISRC2_HB0 = PAGE_ADDR(PAGE_11, 0x40), ISRC2_PB0 = PAGE_ADDR(PAGE_11, 0x43), ACP_HB0 = PAGE_ADDR(PAGE_11, 0x60),
  ACP_PB0 = PAGE_ADDR(PAGE_11, 0x63), OTP_TX0 = PAGE_ADDR(PAGE_12, 0x97), OTP_TX1 = PAGE_ADDR(PAGE_12, 0x98), OTP_TX2 = PAGE_ADDR(PAGE_12, 0x99),
  OTP_TX3 = PAGE_ADDR(PAGE_12, 0x9A), OTP_TX33 = PAGE_ADDR(PAGE_12, 0xB8), GMD_0_HB0_RW = PAGE_ADDR(PAGE_13, 0x00), GMD_0_PB0_RW = PAGE_ADDR(PAGE_13, 0x03),
  GMD_CONTROL_RW = PAGE_ADDR(PAGE_13, 0x1F), GMD_1_HB0_RW = PAGE_ADDR(PAGE_13, 0x20), GMD_1_PB0_RW = PAGE_ADDR(PAGE_13, 0x23), INVALID_REG = PAGE_ADDR(PAGE_INVALID, 0xFF),
  CURPAGE = PAGE_ADDR(PAGE_INVALID, 0xFF)
}
 HDMI Core Registers Enumeration. More...
 
enum  feat_support {
  FEAT_HDCP = 0, FEAT_SCALER = 1, FEAT_AUDIO_OBA = 2, FEAT_AUDIO_DST = 3,
  FEAT_AUDIO_HBR = 4, FEAT_HDMI_1_1 = 5, FEAT_HDMI_1_2A = 6, FEAT_HDMI_1_3A = 7,
  FEAT_DEEP_COLOR_30 = 8, FEAT_DEEP_COLOR_36 = 9, FEAT_DEEP_COLOR_48 = 11, FEAT_UPSAMPLER = 12,
  FEAT_DOWNSAMPLER = 13, FEAT_COLOR_CONVERSION = 14
}
 Supported feature enumeration. More...
 
enum  vs_fsync { VS_FSYNC_EACH_FRAME = 0, VS_FSYNC_ONCE = 1 }
 Frame Sync. More...
 
enum  vs_src { VS_SRC_INTERNAL = 0, VS_SRC_EXTERNAL = 1 }
 
enum  vs_tgl {
  VS_TGL_TABLE = 0, VS_TGL_UNUSED_1 = 1, VS_TGL_UNUSED_2 = 2, VS_TGL_UNUSED_3 = 3,
  VS_TGL_NO_ACTION = 4, VS_TGL_HS = 5, VS_TGL_VS = 6, VS_TGL_HS_VS = 7
}
 
enum  tda998x_vert_freq {
  VFREQ_24Hz = 0, VFREQ_25Hz = 1, VFREQ_30Hz = 2, VFREQ_50Hz = 3,
  VFREQ_59Hz = 4, VFREQ_60Hz = 5
}
 Vertical output frequencies. More...
 
enum  tda998x_pix_edge { PIXEDGE_CLK_POS = 0, PIXEDGE_CLK_NEG = 1 }
 
enum  tda998x_color_space { CS_RGB_FULL = 0, CS_RGB_LIMITED = 1, CS_YUV_ITU_BT601 = 2, CS_YUV_ITU_BT709 = 3 }
 

Functions

static int tda998x_aud_set_pkt_infoframe (struct tda998x_dev *dev, struct tda998x_aud_if_pkt *pkt, bool en)
 Set Audio Infoframe Packet. More...
 
static int tda998x_mtx_set_conv (struct tda998x_dev *dev, enum tda998x_vid_fmt vin_fmt, enum tda998x_vidin_mode vin_mode, enum tda998x_vid_fmt vout_fmt, enum tda998x_vidout_mode vout_mode, enum tda998x_vqr vqr)
 Set Matrix Conversion. More...
 
static int tda998x_mtx_set_mode (struct tda998x_dev *dev, enum mtx_cntrl_bp bp, enum mtx_cntrl_scale sc)
 Set Matrix Mode. More...
 
static int tda998x_write (struct tda998x_dev *dev, enum tda998x_hdmi_reg reg, uint8_t len, uint8_t *data)
 Write Data. More...
 
static int write_reg (struct tda998x_dev *dev, enum tda998x_hdmi_reg reg, uint8_t data)
 Write Register. More...
 
static int write_reg16 (struct tda998x_dev *dev, enum tda998x_hdmi_reg reg, uint16_t data)
 Write 16-bit Register. More...
 
static int tda998x_read (struct tda998x_dev *dev, enum tda998x_hdmi_reg reg, uint8_t len, uint8_t *data)
 Read Data. More...
 
static int read_reg (struct tda998x_dev *dev, enum tda998x_hdmi_reg reg, uint8_t *data)
 Read Register. More...
 
static int write_reg_mask (struct tda998x_dev *dev, enum tda998x_hdmi_reg reg, uint8_t mask, uint8_t val)
 Register Mask Write Write a value with mask bits to a register. More...
 
static int tda998x_cec_write (struct tda998x_dev *dev, enum tda998x_cec_reg reg, uint8_t len, uint8_t *data)
 CEC Write Data. More...
 
static int cec_write_reg (struct tda998x_dev *dev, enum tda998x_cec_reg reg, uint8_t data)
 CEC Write Register. More...
 
static int tda998x_cec_read (struct tda998x_dev *dev, enum tda998x_cec_reg reg, uint8_t len, uint8_t *data)
 CEC Read Data. More...
 
static int cec_read_reg (struct tda998x_dev *dev, enum tda998x_cec_reg reg, uint8_t *data)
 CEC Read Register. More...
 
static int cec_write_reg_mask (struct tda998x_dev *dev, enum tda998x_cec_reg reg, uint8_t mask, uint8_t val)
 CEC Register Mask Write Write a specified value with specified mask bits to a register. More...
 
static uint8_t set_pix_clk (enum tda998x_vid_fmt fmt, enum tda998x_vert_freq freq, uint8_t *pclk)
 
static const struct vidfmt_desc * get_vidfmt_desc (enum tda998x_vid_fmt vid_fmt)
 
static int set_de_vs (struct tda998x_dev *dev, enum tda998x_vid_fmt vout_fmt, enum tda998x_format_3d format_3d)
 
static int set_pix_repeat (struct tda998x_dev *dev, enum tda998x_vid_fmt vout_fmt, uint8_t pix_rpt, enum tda998x_format_3d format_3d)
 Set Pixel Repetition. More...
 
static int set_sampling (struct tda998x_dev *dev)
 
static uint8_t chksum (uint8_t *data, int len)
 
static int set_video_config (struct tda998x_dev *dev, struct tda998x_vid_frm *vid)
 Set Video Configuration. More...
 
int tda998x_aud_set_port_enable (struct tda998x_dev *dev, uint8_t en)
 Set Audio Port Enable. More...
 
int tda998x_aud_set_clk_enable (struct tda998x_dev *dev, uint8_t en)
 Set Audio Clock Port Enable. More...
 
int tda998x_aud_reset_cts (struct tda998x_dev *dev)
 Reset Audio CTS. More...
 
static int tda998x_aud_set_config (struct tda998x_dev *dev, enum tda998x_aud_fmt aud_fmt, enum tda998x_aud_i2s_fmt i2s_fmt, uint8_t i2s_chan, uint8_t dsd_chan, enum tda998x_clkpol_dsd dsd_clkpol, enum tda998x_swap_dsd dsd_swap, uint8_t layout, uint16_t latency, enum tda998x_dst_rate dst_rate)
 Set Audio Input Configuration. More...
 
static int tda998x_aud_set_cts (struct tda998x_dev *dev, enum tda998x_cts_ref cts_ref, enum tda998x_aud_rate afs, enum tda998x_vid_fmt vout_fmt, enum tda998x_vert_freq vout_freq, uint32_t cts, uint16_t ctsX, enum tda998x_ctsk ctsK, enum tda998x_ctsm ctsM, enum tda998x_dst_rate dst_rate)
 Set Audio CTS. More...
 
static int tda998x_aud_set_chan_status (struct tda998x_dev *dev, uint8_t pcm_id, uint8_t fmt_info, uint8_t copyright, uint8_t categoryCode, enum tda998x_aud_rate samp_freq, uint8_t clk_acc, uint8_t maxword_len, uint8_t word_len, uint8_t origsamp_freq)
 Set Audio Output Channel Status. More...
 
static int tda998x_aud_set_chan_status_mapping (struct tda998x_dev *dev, uint8_t src_left[4], uint8_t chan_left[4], uint8_t src_right[4], uint8_t chan_right[4])
 Set Audio Channel Status Mapping. More...
 
static int tda998x_aud_set_mute (struct tda998x_dev *dev, bool mute)
 Set Audio Mute. More...
 
int tda998x_aud_set_input (struct tda998x_dev *dev, struct tda998x_audin_cfg *audin_cfg)
 
int tda998x_get_hotplug_status (struct tda998x_dev *dev, enum tda998x_hotplug_status *status, bool client)
 
static int request_edid_block (struct tda998x_dev *dev)
 
int tda998x_read_edid (struct tda998x_dev *dev, uint8_t *data)
 
int tda998x_edid_get_block (struct tda998x_dev *dev, uint8_t *block, int nblocks, int len)
 Get EDID Block Data. More...
 
static int clear_edid_request (struct tda998x_dev *dev)
 
int edid_block_available (struct tda998x_dev *dev, bool *pSendEDIDCallback)
 
static int tda998x_set_tmds_output (struct tda998x_dev *dev, enum buffer_out_srl_force tmds)
 Set TMDS Output. More...
 
static int tda998x_vidin_set_blanking (struct tda998x_dev *dev, enum vip_cntrl_4_blnkit src, enum vip_cntrl_4_blc code)
 Set Video Input Blanking Source and Code. More...
 
static int tda998x_vidin_set_config (struct tda998x_dev *dev, enum tda998x_vidin_mode vin_mode, enum tda998x_vid_fmt vout_fmt, enum tda998x_format_3d format_3d, enum tda998x_pix_edge edge, enum tda998x_pix_rate pix_rate, enum tda998x_upsample upsampleMode)
 
static int tda998x_vidin_set_fine (struct tda998x_dev *dev, enum vip_cntrl_3_sp_sync sp_sync, uint8_t sp_cnt, enum vip_cntrl_5_clkpol clkpol)
 Set Video Input Fine. More...
 
static int tda998x_vidin_set_mapping (struct tda998x_dev *dev, const enum vip_cntrl_swap *swap, const enum vip_cntrl_mirr *mirr)
 Set Video Input Port Mapping. More...
 
static int tda998x_vidin_set_port_enable (struct tda998x_dev *dev)
 Set Video Input Port Pin Enable. More...
 
static int tda998x_vidin_set_sync (struct tda998x_dev *dev, enum vip_cntrl_3_emb emb, enum tbg_cntrl_0_sync_mthd mthd, bool tgl_v, bool tgl_h, bool tgl_x, uint16_t ref_pix, uint16_t ref_line)
 Set Video Input Synchronization. More...
 
static int tda998x_vidout_enable (struct tda998x_dev *dev, bool en)
 Video Output Enable. More...
 
static int tda998x_vidout_set_config (struct tda998x_dev *dev, enum tda998x_sink sink, enum tda998x_vidout_mode vout_mode, enum hvf_cntrl_0_prefil prefil, enum hvf_cntrl_1_yuv_blk yuv_blk, enum hvf_cntrl_1_vqr vqr)
 Set Video Output Configuration. More...
 
static int tda998x_vidout_set_sync (struct tda998x_dev *dev, bool h_ext, bool v_ext, bool de_ext, uint8_t tgl, enum tbg_cntrl_0_sync sync)
 Set Video Output Synchronization. More...
 
static int tda998x_video_set_inout (struct tda998x_dev *dev, enum tda998x_vid_fmt vin_fmt, enum tda998x_format_3d format_3d, enum tda998x_scaler_mode sca_mod_req, enum tda998x_vid_fmt vout_fmt, uint8_t pix_rpt, enum tda998x_mtx_mode mtx_mode, enum tda998x_dwidth dwidth, enum tda998x_vqr vqr)
 
static int tda998x_mtx_set_coeffs (struct tda998x_dev *dev, struct tda998x_mtx_coeff *mtx)
 Set Matrix Coefficients. More...
 
static int tda998x_mtx_set_inoffset (struct tda998x_dev *dev, struct mtx_offset *offset)
 Set Matrix Input Offset. More...
 
static int tda998x_mtx_set_outoffset (struct tda998x_dev *dev, struct mtx_offset *offset)
 Set Matrix Output Offset. More...
 
static int tda998x_set_aud_pkt_enable (struct tda998x_dev *dev, bool en)
 Set Audio Clock Packet Recovery.
 
static int tda998x_set_pkt_acp (struct tda998x_dev *dev, struct tda998x_pkt *pkt, unsigned int len, uint8_t uAcpType, bool en)
 
static int tda998x_PktSetGeneralCntrl (struct tda998x_dev *dev, bool mute, bool en)
 
static int tda998x_PktSetIsrc1 (struct tda998x_dev *dev, struct tda998x_pkt *pkt, unsigned int len, bool bIsrcCont, bool bIsrcValid, uint8_t uIsrcStatus, bool en)
 
static int tda998x_PktSetIsrc2 (struct tda998x_dev *dev, struct tda998x_pkt *pkt, unsigned int len, bool en)
 
static int tda998x_PktSetMpegInfoframe (struct tda998x_dev *dev, struct tda998x_mpeg_pkt *pkt, bool en)
 
static int tda998x_pkt_set_null_insert (struct tda998x_dev *dev, bool en)
 Set Null Packet Insertion. More...
 
static int tda998x_pkt_set_null (struct tda998x_dev *dev)
 
static int tda998x_pkg_set_spdinfo (struct tda998x_dev *dev, struct tda998x_spd_pkt *pkt, bool en)
 Set Source Product Description Infoframe.
 
static int tda998x_pkt_set_raw_vid_infoframe (struct tda998x_dev *dev, struct tda998x_pkt *pkt, bool en)
 
static int tda998x_pkt_set_vs_infoframe (struct tda998x_dev *dev, struct tda998x_pkt *pkt, unsigned int len, uint8_t version, bool en)
 
static int tda998x_set_pix_edge (struct tda998x_dev *dev, enum vip_cntrl_3_edge edge)
 
static int input_config (struct tda998x_dev *dev, enum tda998x_vidin_mode vin_mode, enum vip_cntrl_3_edge edge, enum tda998x_pix_rate pix_rate, enum tda998x_upsample upsample_mode, uint8_t pix_rpt, enum tda998x_vid_fmt vout_fmt, enum tda998x_format_3d format_3d)
 Configure Video Input. More...
 
static int tda998x_reset (struct tda998x_dev *dev)
 
int tda998x_init (struct tda998x_dev *dev, struct tda998x_cfg *cfg)
 
int tda998x_set_input_output (struct tda998x_dev *dev, struct tda998x_vidin_cfg *vidin_cfg, struct tda998x_vidout_cfg *vidout_cfg, struct tda998x_audin_cfg *audin_cfg, enum tda998x_sink sink)
 Set Input and Output. More...
 
int hot_plug_restore (struct tda998x_dev *dev)
 
int tda998x_handle_interrupt (struct tda998x_dev *dev)
 

Variables

static enum vip_cntrl_swap port_map_rgb444 []
 
static enum vip_cntrl_mirr mirr_map_rgb444 []
 
struct reg_mask_val pll_cfg_common []
 
struct reg_mask_val pll_cfg_other []
 
struct reg_mask_val pll_cfg_480ix576i []
 
static const uint8_t mtx_cfg_preset [12][31]
 
static const struct vidfmt_desc vidformat_desc []
 
struct tda998x_vid_frm vidformat_pc []
 
static const struct vidfmt_map vidformat_map []
 

Detailed Description

TDA998x HDMI Transmitter FreeBSD.

Author
R. Bush bush@.nosp@m.krtk.nosp@m.l.com
Version
v1.0
Date
2017 November 10 Copyright (c) 2017, krtkl inc. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

The views and conclusions contained in the software and documentation are those of the authors and should not be interpreted as representing official policies, either expressed or implied, of the FreeBSD Project.