TDA998x Audio

Functions
int	tda998x_aud_set_port_enable (struct tda998x_dev *dev, uint8_t en)
	Set Audio Port Enable. More...
int	tda998x_aud_set_clk_enable (struct tda998x_dev *dev, uint8_t en)
	Set Audio Clock Port Enable. More...
int	tda998x_aud_reset_cts (struct tda998x_dev *dev)
	Reset Audio CTS. More...
static int	tda998x_aud_set_config (struct tda998x_dev *dev, enum tda998x_aud_fmt aud_fmt, enum tda998x_aud_i2s_fmt i2s_fmt, uint8_t i2s_chan, uint8_t dsd_chan, enum tda998x_clkpol_dsd dsd_clkpol, enum tda998x_swap_dsd dsd_swap, uint8_t layout, uint16_t latency, enum tda998x_dst_rate dst_rate)
	Set Audio Input Configuration. More...
static int	tda998x_aud_set_cts (struct tda998x_dev *dev, enum tda998x_cts_ref cts_ref, enum tda998x_aud_rate afs, enum tda998x_vid_fmt vout_fmt, enum tda998x_vert_freq vout_freq, uint32_t cts, uint16_t ctsX, enum tda998x_ctsk ctsK, enum tda998x_ctsm ctsM, enum tda998x_dst_rate dst_rate)
	Set Audio CTS. More...
static int	tda998x_aud_set_chan_status (struct tda998x_dev *dev, uint8_t pcm_id, uint8_t fmt_info, uint8_t copyright, uint8_t categoryCode, enum tda998x_aud_rate samp_freq, uint8_t clk_acc, uint8_t maxword_len, uint8_t word_len, uint8_t origsamp_freq)
	Set Audio Output Channel Status. More...
static int	tda998x_aud_set_chan_status_mapping (struct tda998x_dev *dev, uint8_t src_left[4], uint8_t chan_left[4], uint8_t src_right[4], uint8_t chan_right[4])
	Set Audio Channel Status Mapping. More...
static int	tda998x_aud_set_mute (struct tda998x_dev *dev, bool mute)
	Set Audio Mute. More...
int	tda998x_aud_set_input (struct tda998x_dev *dev, struct tda998x_audin_cfg *audin_cfg)

Detailed Description

Function Documentation

tda998x_aud_reset_cts()

int tda998x_aud_reset_cts

(

struct tda998x_dev *

dev

)

#include <projects/lib/tda998x.c>

Reset Audio CTS.

Todo:

Finish register mask write sequence to reset CTS

Parameters

dev	TDA998x device structure pointer

Returns

0 on success, non-zero error status otherwise

Todo:

Define reset register table

{
    /* Reset and release the CTS generator */
//  return write_reg_mask_table(dev, &kResetCtsGenerator[0]);
    return 0;
}

tda998x_aud_set_chan_status()

static int tda998x_aud_set_chan_status ( struct tda998x_dev *  dev, uint8_t  pcm_id, uint8_t  fmt_info, uint8_t  copyright, uint8_t  categoryCode, enum tda998x_aud_rate  samp_freq, uint8_t  clk_acc, uint8_t  maxword_len, uint8_t  word_len, uint8_t  origsamp_freq  )

static

#include <projects/lib/tda998x.c>

Set Audio Output Channel Status.

Parameters

dev	TDA998x device structure pointer

Returns

0 on success, non-zero error status otherwise

{
    int ret;
    uint8_t buf[4];
    const uint8_t freq[] = {
        3,      /* 32k */
        0,      /* 44.1k */
        2,      /* 48k */
        8,      /* 88.2k */
        10,     /* 96k */
        12,     /* 176.4k */
        14,     /* 192k */
        9,      /* 768k */
        1,      /* Not indicated */
    };

    /* Return if sink is not an HDMI device */
    if (dev->sink != SINK_HDMI)
        return ERR_NOT_PERMITTED;

    buf[0] = ((uint8_t) fmt_info << 3) |
            ((uint8_t) copyright << 2) |
            ((uint8_t) pcm_id << 1);
    buf[1] = categoryCode;
    buf[2] = ((uint8_t) clk_acc << 4) | freq[samp_freq];
    buf[3] = ((uint8_t) origsamp_freq << 4) |
            ((uint8_t) word_len << 1) |
            (uint8_t) maxword_len;

    /* Write 4 Channel Status bytes */
    ret = tda998x_write(dev, CH_STAT_B_0, 4, &buf[0]);
    if (ret < 0)
        return ret;

    return 0;
}

tda998x_aud_set_chan_status_mapping()

static int tda998x_aud_set_chan_status_mapping ( struct tda998x_dev *  dev, uint8_t  src_left[4], uint8_t  chan_left[4], uint8_t  src_right[4], uint8_t  chan_right[4]  )

static

#include <projects/lib/tda998x.c>

Set Audio Channel Status Mapping.

Parameters

dev	TDA998x device structure pointer
src_left	Left channel source
chan_left	Left channel output
src_right	Right channel source
chan_right	Right channel output

Returns

0 on success, non-zero error status otherwise

{
    int ret;
    uint8_t buf[2];

    if (dev->sink != SINK_HDMI)
        return ERR_NOT_PERMITTED;
 
    buf[0] = (chan_left[0] << 4) | (src_left[0] & 0xFF);
    buf[1] = (chan_right[0] << 4) | (src_right[0] & 0xFF);

    ret = tda998x_write(dev, CH_STAT_B_2_AP0_L, 2, &buf[0]);
    if (ret < 0)
        return ret;
  
    return 0;
}

tda998x_aud_set_clk_enable()

int tda998x_aud_set_clk_enable	(	struct tda998x_dev *	dev,
		uint8_t	en
	)

#include <projects/lib/tda998x.c>

Set Audio Clock Port Enable.

Parameters

dev	TDA998x device structure pointer
en	Clock port enable register value

Returns

0 on success, non-zero error status otherwise

{
    int ret;

    /* Check parameter */
    if (dev == NULL)
        return ERR_NULL_PARAM;

    ret = write_reg(dev, ENA_ACLK, en);
    if (ret < 0)
        return ret;

    return 0;
}

tda998x_aud_set_config()

static int tda998x_aud_set_config ( struct tda998x_dev *  dev, enum tda998x_aud_fmt  aud_fmt, enum tda998x_aud_i2s_fmt  i2s_fmt, uint8_t  i2s_chan, uint8_t  dsd_chan, enum tda998x_clkpol_dsd  dsd_clkpol, enum tda998x_swap_dsd  dsd_swap, uint8_t  layout, uint16_t  latency, enum tda998x_dst_rate  dst_rate  )

static

#include <projects/lib/tda998x.c>

Set Audio Input Configuration.

Parameters

dev	TDA998x device structure pointer

Returns

0 on success, non-zero error status otherwise

{
    int ret;
    uint8_t reg_val;

    switch (aud_fmt) {
    case AFMT_SPDIF:
        reg_val = (uint8_t) REG_VAL_SEL_AIP_SPDIF;

        /* configure MUX_AP */
        ret = write_reg(dev, MUX_AP, MUX_AP_SELECT_SPDIF);
        if (ret < 0)
            return ret;

        break;

    case AFMT_I2S:
        reg_val = (uint8_t) REG_VAL_SEL_AIP_I2S;
    
        /* configure MUX_AP */
        ret = write_reg(dev, MUX_AP, MUX_AP_SELECT_I2S);
        if (ret < 0)
            return ret;
    
        break;
 
    case AFMT_OBA:
        reg_val = (uint8_t) REG_VAL_SEL_AIP_OBA;
        break;
 
    case AFMT_HBR:
        reg_val = (uint8_t) REG_VAL_SEL_AIP_HBR;
        break;
 
    default:
        return ERR_BAD_PARAM;
    }

    /* Set the audio input processor format to aud_fmt. AIP_CLKSEL_sel_aip */
    ret = write_reg_mask(dev, AIP_CLKSEL, 0x38U, reg_val << 3);
    if (ret < 0)
        return ret;
  
    /* Channel status on 1 channel  */
    ret = write_reg_mask(dev, CA_I2S, CA_I2S_HBR_CHSTAT_4, 0);
    if (ret < 0)
        return ret;
  
    /* Select the audio format */
    if (aud_fmt == AFMT_I2S) {
        if (i2s_chan != 32) {
            ret = write_reg_mask(dev,
                    CA_I2S,
                    CA_I2S_CA_I2S_MASK,
                    (uint8_t) i2s_chan);
        }
    
        /* Select the I2S format */
        ret = write_reg_mask(dev,
                I2S_FORMAT,
                I2S_FORMAT_I2S_FORMAT_MASK,
                (uint8_t) i2s_fmt);
        if (ret < 0)
            return ret;
  
    } else if (aud_fmt == AFMT_OBA) {
        ret = write_reg(dev, CA_DSD, dsd_chan);
        if (ret < 0)
            return ret;
 
        ret = write_reg_mask(dev,
                AIP_CLKSEL,
                AIP_CLKSEL_SEL_POL_CLK,
                (uint8_t) dsd_clkpol);
            if (ret < 0)
                return ret;

        ret = write_reg_mask(dev,
                AIP_CNTRL_0,
                AIP_CNTRL_0_SWAP,
                (uint8_t) dsd_swap);
        if (ret < 0)
            return ret;
    }
 
    /* Set layout and latency */
    ret = write_reg_mask(dev,
            AIP_CNTRL_0,
            AIP_CNTRL_0_LAYOUT,
            layout << 2);
    if (ret < 0)
        return ret;

    ret = write_reg(dev, LATENCY_RD, (uint8_t) latency);
    if (ret < 0)
        return ret;

    return 0;
}

tda998x_aud_set_cts()

static int tda998x_aud_set_cts ( struct tda998x_dev *  dev, enum tda998x_cts_ref  cts_ref, enum tda998x_aud_rate  afs, enum tda998x_vid_fmt  vout_fmt, enum tda998x_vert_freq  vout_freq, uint32_t  cts, uint16_t  ctsX, enum tda998x_ctsk  ctsK, enum tda998x_ctsm  ctsM, enum tda998x_dst_rate  dst_rate  )

static

#include <projects/lib/tda998x.c>

Set Audio CTS.

Parameters

dev	TDA998x device structure pointer

Returns

0 on success, non-zero error status otherwise

Todo:

Define CTS values

Todo:

Reset and release the CTS generator

{
    int ret;
    uint8_t reg_val;
    uint8_t pixClk;         /* Pixel clock index */
    uint32_t acrN;          /* Audio clock recovery N */
 
    /* Return if sink is not an HDMI device */
    if (dev->sink != SINK_HDMI)
        return ERR_NOT_PERMITTED;
 
    if ((vout_fmt >= VFMT_01_640x480p_60Hz) &&
            (vout_fmt <= VFMT_62_1280x720p_30Hz)) {
        if (vout_freq == VFREQ_50Hz) {
            if ((vout_fmt < VFMT_17_720x576p_50Hz) ||
                    (vout_fmt > VFMT_31_1920x1080p_50Hz))
                return ERR_ILLEGAL_PARAMS;
    
        } else if (vout_freq == VFREQ_24Hz) {
            if ((vout_fmt != VFMT_32_1920x1080p_24Hz) &&
                    (vout_fmt != VFMT_60_1280x720p_24Hz))
                return ERR_ILLEGAL_PARAMS;
        } else if (vout_freq == VFREQ_25Hz) {
            if ((vout_fmt != VFMT_33_1920x1080p_25Hz) &&
                    (vout_fmt != VFMT_20_1920x1080i_50Hz) &&
                    (vout_fmt != VFMT_61_1280x720p_25Hz))
                return ERR_ILLEGAL_PARAMS;
        } else if (vout_freq == VFREQ_30Hz) {
            if ((vout_fmt != VFMT_34_1920x1080p_30Hz) &&
                    (vout_fmt != VFMT_05_1920x1080i_60Hz) &&
                    (vout_fmt != VFMT_62_1280x720p_30Hz))
                return ERR_ILLEGAL_PARAMS;
        } else {
            if (vout_fmt >= VFMT_17_720x576p_50Hz)
                return ERR_ILLEGAL_PARAMS;
        }
    }
  
    /* Check for auto or manual CTS */
    if (cts == 0) {
        /* Auto */
        ret = write_reg_mask(dev, AIP_CNTRL_0, AIP_CNTRL_0_ACR_MAN, 0);
        if (ret < 0)
            return ret;
    } else {
        /* Manual */
        ret = write_reg_mask(dev,
                AIP_CNTRL_0,
                AIP_CNTRL_0_ACR_MAN,
                AIP_CNTRL_0_ACR_MAN);
        if (ret < 0)
            return ret;
    }
 
    /* Derive M and K from X? */
    if ((ctsM == CTSMTS_USE_CTSX) ||
            (ctsK == CTSK_USE_CTSX)) {
//      ctsM = (enum tda998x_ctsm) kCtsXToMK[ctsX][0];
//      ctsK = (enum tda998x_ctsk) kCtsXToMK[ctsX][1];
    }
 
    /* Set the Post-divider measured timestamp factor */
    reg_val = (uint8_t) ctsM;
    ret = write_reg_mask(dev,
            CTS_N_RW,
            CTS_N_M_SEL_MASK,
            reg_val << 4);
    if (ret < 0)
        return ret;
 
    /* Set the predivider scale */
    ret = write_reg_mask (dev,
            CTS_N_RW,
            CTS_N_K_SEL_MASK,
            (uint8_t) ctsK);
    if (ret < 0)
        return ret;

    /*
     * Use vout_fmt and vout_freq to index into a lookup table to get
     * the current pixel clock value.
     */
    set_pix_clk(vout_fmt, vout_freq, &pixClk);

    /*
     * Set the Audio Clock Recovery N multiplier based on the audio sample
     * frequency afs and current pixel clock.
     */
//  acrN = kPixClkToAcrN[pixClk][afs];
//   /* HDMITX_AFS_32k  _AFS_48K       _AFS_96K        _AFS_192K */
//   /*         _AFS_44_1k      _AFS_88_2K      _AFS_176_4K       */
//     { 4576,   7007,   6864,  14014,  13728,  28028,  27456}, /* E_PIXCLK_25175 */
//     { 4096,   6272,   6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_25200 */
//     { 4096,   6272,   6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_27000 */
//     { 4096,   6272,   6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_27027 */
//     { 4096,   6272,   6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_54000 */
//     { 4096,   6272,   6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_54054 */
//     { 4096,   6272,   6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_59400 */
//     {11648,  17836,  11648,  35672,  23296,  71344,  46592}, /* E_PIXCLK_74175 */
//     { 4096,   6272,   6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_74250 */
//     {11648,   8918,   5824,  17836,  11648,  35672,  23296}, /* E_PIXCLK_148350*/
//     { 4096,   6272,   6144,  12544,  12288,  25088,  24576}  /* E_PIXCLK_148500*/
//  #ifdef FORMAT_PC
//    ,{ 4096,  6272,  6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_31500 */
//     { 4096,  6272,  6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_36000 */
//     { 4096,  6272,  6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_40000 */
//     { 4096,  6272,  6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_49500 */
//     { 4096,  6272,  6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_50000 */
//     { 4096,  6272,  6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_56250 */
//     { 4096,  6272,  6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_65000 */
//     { 4096,  6272,  6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_75000 */
//     { 4096,  6272,  6144,  12544,  12288,  25088,  24576}, /* E_PIXCLK_78750 */
//     { 4096,  6272,  6144,  12544,  12288,  25088,  24576},  /* E_PIXCLK_162000*/
//     { 4096,  6272,  6144,  12544,  12288,  25088,  24576}  /* E_PIXCLK_157500*/
//  #endif /* FORMAT_PC */
//  };

    acrN = 6272;
    /* Set ACR N multiplier [19 to 16] */
    reg_val = (uint8_t) (acrN >> 16);
    ret = write_reg (dev, ACR_N_2, reg_val);
    if (ret < 0)
        return ret;

    /* Set ACR N multiplier [15 to 8] */
    reg_val = (uint8_t) (acrN >> 8);
    ret = write_reg (dev, ACR_N_1, reg_val);
    if (ret < 0)
        return ret;

    /* Set ACR N multiplier [7 to 0] */
    reg_val = (uint8_t) acrN;
    ret = write_reg (dev, ACR_N_0, reg_val);
    if (ret < 0)
        return ret;

    /*
     * Set the CDC Audio Divider register based on the audio sample frequency
     * afs and current pixel clock.
     */
//  reg_val = kPixClkToAdiv[pixClk][afs];
//  {
//   /* HDMITX_AFS_32k  _AFS_48K       _AFS_96K        _AFS_192K */
//   /*         _AFS_44_1k      _AFS_88_2K      _AFS_176_4K       */
//     {2,      2,      2,      1,      1,      0,      0},     /* E_PIXCLK_25175 */
//     {2,      2,      2,      1,      1,      0,      0},     /* E_PIXCLK_25200 */
//     {2,      2,      2,      1,      1,      0,      0},     /* E_PIXCLK_27000 */
//     {2,      2,      2,      1,      1,      0,      0},     /* E_PIXCLK_27027 */
//     {3,      3,      3,      2,      2,      1,      1},     /* E_PIXCLK_54000 */
//     {3,      3,      3,      2,      2,      1,      1},     /* E_PIXCLK_54054 */
//     {3,      3,      3,      2,      2,      1,      1},     /* E_PIXCLK_59400 */
//     {4,      3,      3,      2,      2,      1,      1},     /* E_PIXCLK_74175 */
//     {4,      3,      3,      2,      2,      1,      1},     /* E_PIXCLK_74250 */
//     {5,      4,      4,      3,      3,      2,      2},     /* E_PIXCLK_148350 */
//     {5,      4,      4,      3,      3,      2,      2}      /* E_PIXCLK_148500 */
//  #ifdef FORMAT_PC
//    ,{2,      2,      2,      1,      1,      0,      0}, /* E_PIXCLK_31500  */
//     {3,      2,      2,      1,      1,      0,      0}, /* E_PIXCLK_36000  */
//     {3,      2,      2,      1,      1,      0,      0}, /* E_PIXCLK_40000  */
//     {3,      3,      3,      2,      2,      1,      1}, /* E_PIXCLK_49500  */
//     {3,      3,      3,      2,      2,      1,      1}, /* E_PIXCLK_50000  */
//     {3,      3,      3,      2,      2,      1,      1}, /* E_PIXCLK_56250  */
//     {4,      3,      3,      2,      2,      1,      1}, /* E_PIXCLK_65000  */
//     {4,      3,      3,      2,      2,      1,      1}, /* E_PIXCLK_75000  */
//     {4,      3,      3,      2,      2,      1,      1}, /* E_PIXCLK_78750  */
//     {5,      4,      4,      3,      3,      2,      2}, /* E_PIXCLK_162000 */
//     {5,      4,      4,      3,      3,      2,      2}  /* E_PIXCLK_157500 */
//  #endif /* FORMAT_PC */
//  };

    ret = write_reg(dev, AUDIO_DIV, 4);
    if (ret < 0)
        return ret;

    /*
     * If auto CTS, get CTS value based on the audio sample
     * frequency afs and current pixel clock.
     */
//  if (cts == 0)
//      cts = kPixClkToAcrCts[pixClk][afs];
 
    /* Set manual or pixel clock CTS */
    if (cts != 0) {
        /* Set manual ACR CTS [19 to 16] */
        reg_val = (uint8_t) (cts >> 16);
        ret = write_reg (dev, ACR_CTS_2, reg_val);
        if (ret < 0)
            return ret;

        /* Set manual ACR CTS [15 to 8] */
        reg_val = (uint8_t) (cts >> 8);
        ret = write_reg (dev, ACR_CTS_1, reg_val);
        if (ret < 0)
            return ret;
 
        /* Set manual ACR CTS [7 to 0] */
        reg_val = (uint8_t) cts;
        ret = write_reg (dev, ACR_CTS_0, reg_val);
        if (ret < 0)
            return ret;
    }

    /* Set the CTS clock reference register according to cts_ref */
    reg_val = (uint8_t) cts_ref;
    ret = write_reg_mask(dev,
            AIP_CLKSEL,
            AIP_CLKSEL_SEL_FS_MASK,
            reg_val);
    if (ret < 0)
        return ret;

//  ret = write_reg_mask_table(dev, &kResetCtsGenerator[0]);
  
    return ret;
}

tda998x_aud_set_input()

int tda998x_aud_set_input	(	struct tda998x_dev *	dev,
		struct tda998x_audin_cfg *	audin_cfg
	)

#include <projects/lib/tda998x.c>

Todo:

Rework the audio configuration

< Number of channels - 1
< Channel allocation code

{
    int ret;
    uint8_t reg_val;
    uint8_t buf[4];
    uint8_t layout;                    /* 0 or 1 */
    uint16_t uCtsX;                    /* CtsX value */
    uint32_t acrN;
    struct tda998x_aud_if_pkt aif_pkt;        /* Audio infoframe packet */
    
    ret = write_reg(dev, ENA_AP, 0xFF);
    if (ret < 0)
        return ret;
    
    ret = write_reg(dev, ENA_ACLK, 0x01);
    if (ret < 0)
        return ret;
    
    /* configure MUX_AP */
    ret = write_reg(dev, MUX_AP, 0x64);
    if (ret < 0)
        return ret;
    
    /* Set the audio input processor format to aFmt. */
    ret = write_reg_mask(dev, AIP_CLKSEL, 0x38, 0x08);
    if (ret < 0)
        return ret;
    
    /* Channel status on 1 channel  */
    ret = write_reg_mask(dev, CA_I2S, (1 << 5), 0);
    if (ret < 0)
        return ret;
    
    ret = write_reg_mask(dev, CA_I2S, 0x1F, 0x1F);
    if (ret < 0)
        return ret;
    
    /* Select the I2S format */
    ret = write_reg_mask(dev, I2S_FORMAT, 0x0F, 0x0E);
    if (ret < 0)
        return ret;
    
    ret = write_reg_mask(dev, AIP_CNTRL_0, (1 << 2), (1 << 2));
    if (ret < 0)
        return ret;
    
    ret = write_reg(dev, LATENCY_RD, 0x80);
    if (ret < 0)
        return ret;
    
    /* Auto */
    ret = write_reg_mask(dev, AIP_CNTRL_0, (1 << 5), 0);
    if (ret < 0)
        return ret;
    
    /* Set the Post-divider measured timestamp factor */
    ret = write_reg_mask(dev, CTS_N_RW, 0x30, 0x10);
    if (ret < 0)
        return ret;
    
    /* Set the Pre-divider scale */
    ret = write_reg_mask(dev, CTS_N_RW, 0x07, 0x01);
    if (ret < 0)
        return ret;
    
    /* Set ACR N multiplier [19 to 16] */
    ret = write_reg(dev, ACR_N_2, 0x00);
    if (ret < 0)
        return ret;
    
    /* Set ACR N multiplier [15 to 8] */
    ret = write_reg(dev, ACR_N_1, 0x18);
    if (ret < 0)
        return ret;
    
    ret = write_reg(dev, ACR_N_0, 0x00);
    if (ret < 0)
        return ret;
    
    /*
     * Set the CDC Audio Divider register based on the audio sample
     * frequency afs and current pixel clock
     */
    ret = write_reg(dev, AUDIO_DIV, 0x04);
    if (ret < 0)
        return ret;
    
    /* Set the CTS clock reference register according to ctsRef */
    ret = write_reg_mask(dev, AIP_CLKSEL, 0x03, 0);
    if (ret < 0)
        return ret;
    
    /* Reset and release the CTS generator */
    ret = write_reg_mask(dev, AIP_CNTRL_0, (1 << 6), (1 << 6));
    if (ret < 0)
        return ret;
    
    ret = write_reg_mask(dev, AIP_CNTRL_0, (1 << 6), 0);
    if (ret < 0)
        return ret;
    
    /* Prepare Byte 0 */
    buf[0] = 0x00; // ((UInt8)formatInfo << 3) | ((UInt8)copyright << 2) | ((UInt8)pcmIdentification<< 1);
    
    /* Prepare Byte 1 */
    buf[1] = 0x00; // categoryCode;
    
    /* Prepare Byte 3  - note Byte 2 not in sequence in TDA9983 register map */
    buf[2] = 0x02; // ((UInt8)clockAccuracy << 4) | 0x02;
    
    /* Prepare Byte 4 */
    buf[3] = (13 << 4) | (1 << 1);
    
    ret = tda998x_write(dev, CH_STAT_B_0, 4, &buf[0]);
    if (ret < 0)
        return ret;
    
    ret = tda998x_aud_set_mute(dev, true);
    if (ret < 0)
        return ret;
    
    /* Wait 20ms */
    usleep(1000 * 20);
    
    ret = tda998x_aud_set_mute(dev, false);
    if (ret < 0)
        return ret;
    
    aif_pkt.nchan = 7;            
    aif_pkt.type = 0;            /* refer to stream header */
    aif_pkt.samp_size = 0;            /* refer to stream header */
    aif_pkt.chan_alloc = audin_cfg->ch_alloc;    
    aif_pkt.lvl_shift = 0;            /* 0dB level shift */
    aif_pkt.dmix_inhib = 0;        /* down-mix stereo permitted */
    aif_pkt.samp_freq = 0;            /* refer to stream header */
    
    ret = tda998x_aud_set_pkt_infoframe(dev, &aif_pkt, true);
    if (ret < 0)
        return ret;
    
    return 0;
}

tda998x_aud_set_mute()

static int tda998x_aud_set_mute ( struct tda998x_dev *  dev, bool  mute  )

static

#include <projects/lib/tda998x.c>

Set Audio Mute.

Parameters

dev	TDA998x device structure pointer
mute	Mute enable value

Returns

0 on success, non-zero error status otherwise

{
    int ret;

    if (dev->sink != SINK_HDMI)
        return ERR_NOT_PERMITTED;
 
    if (mute) {
        ret = write_reg_mask(dev,
                SR_REG,
                SR_REG_SR_AUDIO,
                SR_REG_SR_AUDIO);
        if (ret < 0)
            return ret;

        ret = write_reg_mask(dev, SR_REG, SR_REG_SR_AUDIO, 0);
        if (ret < 0)
            return ret;
    }
 
    ret = write_reg_mask(dev,
            AIP_CNTRL_0,
            AIP_CNTRL_0_RST_FIFO,
            mute ? AIP_CNTRL_0_RST_FIFO : 0);
    if (ret < 0)
        return ret;
 
    return 0;
}

tda998x_aud_set_port_enable()

int tda998x_aud_set_port_enable	(	struct tda998x_dev *	dev,
		uint8_t	en
	)

#include <projects/lib/tda998x.c>

Set Audio Port Enable.

Lookup table for each pixel clock frequency's CTS value in kHz according to SCS table "Audio Clock Recovery CTS Values" Lookup table for each pixel clock frequency's Audio Clock Regeneration N, according to SCS Table "Audio Clock Recovery N Values" Lookup table for each pixel clock frequency's Audio Divider, according to SCS Table "Audio Clock Recovery Divider Values" Lookup table for converting a sampling frequency into the values required in channel status byte 3 according to IEC60958-3 Lookup table for each CTS X factor's k and m register values Table of registers to reset and release the CTS generator

Parameters

dev	TDA998x device structure pointer
en	Audio port enable register value

Returns

0 on success, non-zero error status otherwise

{
    int ret;

    /* Check parameter */
    if (dev == NULL)
        return ERR_NULL_PARAM;

    ret = write_reg(dev, ENA_AP, en);
    if (ret < 0)
        return ret;

    return 0;
}